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TLV7022DGKR

Texas Instruments TLV7022DGKR

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Price
RoHS Y Compliant Compliant Y Y Y Y Compliant Y Y
Lead Status Y Yes Yes Y Y Y Y Yes Y Y
Features Fail-safe,Hysteresis,POR Cost Optimized,EMI Hardened,Low Power,Shutdown,Small Size EMI Hardened,MUX Friendly,Small Size Fail-safe,Hysteresis,POR Fail-safe,Hysteresis,POR Cost Optimized,EMI Hardened,Small Size Cost Optimized,EMI Hardened,Small Size
Input bias current ()(max)(nA) 0.002 0.002 0.002
Iq per channel(typ)(mA) 0.0047 0.01 2.4 0.0003 0.0003 0.06 0.06
Number of channels 2 1 2 2 2 4 4
Operating temperature range(C) -40 -40 -40 -40 -40 -40 -40
Output type Open-collector,Open-drain Open-collector,Open-drain Open-collector,Open-drain
Package area(mm^2) 14.7 0.64 4 8.12 14.7 13.692 9
Package size (L x W)(mm) 3 x 4.9 0.8 x 0.8 2 x 2 2.9 x 2.8 3 x 4.9 4.2 x 3.26 3 x 3
Package type VSSOP X2SON WSON SOT-23-THN VSSOP SOT-23-THN WQFN
Pin count 8 5 8.0 8 8 14.0 16.0
Propagation delay time(s) 0.26 3 3
Rail-to-rail In In,Out In,Out In In In,Out In,Out
Rating Catalog Catalog Catalog Catalog Catalog Catalog Catalog
TI functional safety category Functional Safety-Capable
VICR(max)(V) 6.6 6.6 6.6
VICR(min)(V) 0 0 0
Vos (offset voltage at 25C)(max)(mV) 8 2.25 1 8 8 1.6 1.6
Vs(max)(V) 6.5 6.5 6.5
Vs(min)(V) 1.6 1.6 1.6
TI.com inventory 5418265 1181895 34993 119295 190275 42712 8960
Approx. price(US$) .275 | 1ku .168 | 1ku .483 | 1ku .33 | 1ku .33 | 1ku .18 | 1ku .2 | 1ku
Accuracy(%) 2 2
Approx. Price (US$) 0.18 1ku 0.18 1ku 0.75 1ku
Output Options Fixed Output Fixed Output
Fixed Output Options(V) 1.8,2.5,3.3 1.8,2.5,3.3
Iq(Typ)(mA) 0.03 0.03
Output Capacitor Type Ceramic Ceramic
ating Catalog Catalog Catalog
Noise(uVrms) 48 48
Operating Temperature ange(C) -40 to 125,-40 to 85 -40 to 125,-40 to 85 -40 to 85
Vin(Min)(V) 2 2
egulated Outputs(#) 1 1
Vout(Max)(V) 3.3 3.3
Vin(Max)(V) 5.5 5.5
Iout(Max)(A) 0.2 0.2
Package Group DSBGA DSBGA SC70,SOT-23
Vout(Min)(V) 1.8 1.8
PS @ 100KHz(dB) 51 51
Vdo(Typ)(mV) 220 220
Additional Features Enable,Overcurrent Protection,Thermal Shutdown Enable,Overcurrent Protection,Thermal Shutdown
Architecture CMOS CMOS CMOS CMOS
CMRR(typ)(dB) 89 110 77 77
GBW(typ)(MHz) 0.35 11 1 1
Input bias current(max)(pA) 12
Input common mode headroom (to negative supply)(typ)(V) 0 0 -0.1 -0.1
Input common mode headroom (to positive supply)(typ)(V) 0 0 0.1 0.1
Iout(typ)(A) 0.04 0.073 0.04 0.04
Offset drift(typ)(V/C) 0.8 0.25 0.6 0.6
Output swing headroom (to negative supply)(typ)(V) 0.02 0.025 0.01 0.01
Output swing headroom (to positive supply)(typ)(V) 0.02 -0.025 -0.01 -0.01
Slew rate(typ)(V/s) 0.2 33 2 2
TI package name DPW DSG DYY RTE
Total supply voltage (+5 V = 5, 5 V = 10)(max)(V) 5.5 16 5.5 5.5
Total supply voltage (+5 V = 5, 5 V = 10)(min)(V) 1.2 2.7 1.8 1.8
Vn at 1 kHz(typ)(nVHz) 66 6.8 30 30
Vos (Offset Voltage @ 25C)(Max)(mV) 12
t ESP Low - to - High(us) 6
Vs(Max)(V) 5.5
Estimated Package Size (WxL)(mm2) [pf]6SC70[/pf]
Vs(Min)(V) 1.8
Iq per channel(Max)(mA) 0.005
Special Features With Voltage eference
Input Bias Current (+/-)(Max)(nA) 0.01
Number of Channels(#) 1
Output Type Push-Pull
VIC (Min)(V) -0.2
ail-to- ail In
VIC (Max)(V) 5.7