10-Bit, 65/80/105 MSPS 3 V A/D Converter Features: Single 3 V supply operation (2.7 V to 3.3 V) SNR = 58 dBc (to Nyquist) SFDR = 77 dBc (to Nyquist) Low Power ADC Core: 96 mW at 65 MSPS 104 mW at 80 MSPS 120 mW at 105 MSPS Differential input with 300 MHz bandwidth On-chip reference and sample-and-hold amplifier DNL = ±0.25 LSB Flexible Analog Input: 1 Vp-p to 2 Vp-p Range Offset binary or twos complement data format Clock Duty Cycle Stabilizer

ADC 10BIT 65MSPS LFCSP-32; Resolution (Bits):10bit; Sampling Rate:65MSPS; Supply Voltage Type:Single; Supply Voltage Min:2.7V; Supply Voltage Max:3.3V; ADC / DAC Case Style:LFCSP; No. of Pins:32Pins; Input Channel Type:Differential; Data Interface:-; Operating Temperature Min:-40°C; Operating Temperature Max:85°C; Packaging:Each; Product Range:Single 10-Bit Pipelined ADCs; Automotive Qualification Standard:-; MSL:MSL 3 - 168 hours; SVHC:No SVHC (20-Jun-2016); Base Number:9215; Conversion Time:15.4ns; IC Case Style:LFCSP; IC Generic Number:9215; Linearity Error ADC / DAC +:0.25LSB; Linearity Error ADC / DAC -:0.25LSB; Logic Function Number:9215; No. of Bits:10bit; No. of Channels:1Channels; Operating Temperature Range:-40°C to +85°C; Signal to Noise Ratio:58dB; Termination Type:Surface Mount Device; Voltage Vcc:3V

The AD9215 is a family of monolithic, single 3 V supply, 10-bit, 65/80/105 MSPS analog-to-digital converters (ADC). This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9215 uses a multistage differential pipelined architecture with output error correction logic to provide 10-bit accuracy at 105 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The wide bandwidth, truly differential sample-and-hold amplifier (SHA) allows for a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9215 is suitable for applications in communications, imaging, and medical ultrasound.A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer compensates for wide variations in the clock duty cycle while maintaining excellent performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range signal indicates an overflow condition, which can be used with the MSB to determine low or high overflow.Fabricated on an advanced CMOS process, the AD9215 is available in both a 28-lead surface-mount plastic package and a 32-lead chip scale package and is specified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTS The AD9215 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. Operating at 105 MSPS, the AD9215 core ADC consumes a low 120 mW; at 80 MSPS, the power dissipation is 104 mW; and at 65 MSPS, the power dissipation is 96 mW. The patented SHA input maintains excellent performance for input frequencies up to 200 MHz and can be configured for single-ended or differential operation. The AD9215 is part of several pin compatible 10-, 12-, and 14-bit low power ADCs. This allows a simplified upgrade from 10 bits to 12 bits for systems up to 80 MSPS. The clock duty cycle stabilizer maintains converter performance over a wide range of clock pulse widths. The out of range (OR) output bit indicates when the signal is beyond the selected input range.APPLICATIONS Ultrasound equipment IF sampling in communications receivers Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes

10-Bit, 65/80/105 MSPS 3 V A/D Converter Features: Single 3 V supply operation (2.7 V to 3.3 V) SNR = 58 dBc (to Nyquist) SFDR = 77 dBc (to Nyquist) Low Power ADC Core: 96 mW at 65 MSPS 104 mW at 80 MSPS 120 mW at 105 MSPS Differential input with 300 MHz bandwidth On-chip reference and sample-and-hold amplifier DNL = ±0.25 LSB Flexible Analog Input: 1 Vp-p to 2 Vp-p Range Offset binary or twos complement data format Clock Duty Cycle Stabilizer

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