LED Single Chip Yellow 590nm 50mA 2-Pin PLCC T/R

Battery Protector Li-Ion/Li-Pol Over Charge/Cell-Balance/Over Discharge Multi-Cell Pack 8-Pin TSSOP T/R

NOR QLHT SPI 128MB

15.6" 4K 12G-SDI WITH WAVEFORM

2 A AC 32 V DC Fuse Board Mount (Cartridge Style Excluded) Surface Mount 0603 (1608 Metric)

The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate frequency (IF) receiver specifically designed to support multiple antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of four high performance ADCs and NSR digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI.With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6657A supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22%, 33%, or 36% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6657A can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode, up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode, or up to 70.0 dBFS SNR for a 65 MHz bandwidth in the 36% mode.With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6657A can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6657A to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are used.After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels.The AD6657A receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board level system testing.The AD6657A is available in a Pb-free, RoHS-compliant, 144 ball, 10 mm × 10 mm chip scale package ball grid array (CSP_BGA) that is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radiosPRODUCT HIGHLIGHTS Four analog-to-digital converters (ADCs) are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 65 MHz at 185 MSPS. LVDS digital output interface configured for low cost FPGA families. 230 mW per ADC core power consumption. 5. Operation from a single 1.8 V supply. Standard SPI that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.

12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator Features:Integrated 19-channel V-driver1.8 V AFETG core24 programmable vertical clock signalsCorrelated double sampler (CDS) with 3 dB, 0 dB, +3 dB, and +6 dB gain12-bit, 40.5 MHz analog-to-digital converter (ADC)Black level clamp with variable level controlComplete on-chip timing generatorPrecision Timing core with ~400 ps resolutionOn-chip 3 V horizontal and RG driversGeneral-purpose outputs (GPOs) for shutter and system supportOn-chip sync generator with external sync inputOn-chip 1.8 V low dropout (LDO)

25 MHz XO (Standard) LVPECL Oscillator 3.3V Enable/Disable 8-SMD, No Lead

FLASH - NOR Memory IC 256Mbit Parallel 108 MHz 80 ns 44-FBGA (7.5x5)

Circular Cable Assembly Shielded 3.28' (1.00m)