Quad, Current-Output, Serial-Input 16-/14-Bit DACs Features: 16-bit resolution INL of ±1 LSB (B Grade) 2 mA full-scale current ± 20%, with VREF = ±10 V 0.9 μs settling time to ±0.1% 12 MHz multiplying bandwidth Midscale glitch of −1 nV-sec Midscale or zero-scale reset Four separate, 4-quadrant multiplying reference inputs Compact 28-lead SSOP and 32-lead LFCSP See data sheet for additional featuresAD5544-EP supports defense and aerospace applications (AQEC standard) Download AD5544-EP Data Sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12663 DSCC Drawing Number

High Common-Mode Voltage, Single-Supply Difference Amplifier

1.6 V, Micropower 12-/10-/8-Bit ADCs

20 V, 500 mA, Low Noise, CMOS LDO Features: Input voltage range: 3.3 V to 20 V Maximum output current: 500 mA Low Noise: 15 μV rms for fixed output versions PSRR Performance of 60 dB at 10 kHz, VOUT = 3.3 V Reverse current protection Low dropout voltage: 350 mV at 500 mA Initial accuracy: ±0.8% Accuracy over line, load, and temperature −2% to +1%, TJ = −40°C to +125°C −1.25% to +1%, TJ = 0°C to +85°C Low quiescent current (VIN = 5 V), IGND = 900 μA with 500 mA load Low shutdown current: <40 μA at VIN = 12 V, stable with small 1 μF ceramic output capacitor 7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 5 V, and 9 V Adjustable output from 1.22 V to VIN − VDO Foldback current limit and thermal overload protection User programmable precision UVLO/enable Power-good indicator 8-lead LFCSP and 8-lead SOIC packages

X-Stream 4.25 Gbps 40 40 Digital Crosspoint Switch Features: DC to 4.25 Gbps per port NRZ data rate Adjustable receive equalization 3 dB, 6 dB, or 12 dB boost Compensates over 40 inches of FR4 at 4.25 Gbps Adjustable transmit preemphasis/deemphasis Programmable boost and output level Compensates over 40 inches of FR4 at 4.25 Gbps Low Power 105 mW per channel at 2.5 V (400 mVP-P differential output level swing) 40 × 40, fully differential, nonblocking array Double rank connection programming with dual maps Low jitter, typically <25 ps Flexible 2.5 V to 3.3 V supply range DC- or ac-coupled differential PECL/CML inputs Differential CML outputs Per-lane polarity inversion for routing ease 50 Ω on-chip I/O termination with disable feature Supports 8b10b, scrambled or uncoded NRZ data Serial (I2C slave or SPI) control interface Parallel control interface

Cascadable IF VGAs with Programmable RMS Detectors

Zero Drift, Digitally Programmable Instrumentation Amplifier

Lithium Ion Battery Monitoring System Features: 12-bit ADC, 1 μs per channel conversion time 6 analog input channels,  CM range 0.5 V to 27.5 V 6 auxiliary ADC Inputs ±1.6 mV cell voltage accuracy On-chip voltage regulator Cell balancing interface Daisy-chain interface Internal reference: ±3 ppm/°C 1.8 μA power-down current High input impedance Serial interface with alert function See data sheet for additional features

250 MHz Bandwidth DPD Observation Receiver

Synchronous Buck Controller with Constant On-Time and Valley Current Mode