The LTC5594 is a direct conversion quadrature demodulator optimized for high linearity zero-IF and low-IF receiver applications in the 300MHz to 9GHz frequency range. The very wide IF bandwidth of more than 1GHz makes the LTC5594 particularly suited for demodulation of very wideband signals, especially in 5G front-haul/back-haul receiver applications. The outstanding dynamic range of the LTC5594 makes the device suitable for demanding infrastructure direct conversion applications. Proprietary technology inside the LTC5594 provides the capability to optimize OIP2 to 65dBm, and achieve image rejection better than 60dB. The DC offset control function allows nulling of the DC offset at the A/D converter input, thereby optimizing the dynamic range of true zero-IF receivers that use DC-coupled IF signal paths. The wideband RF and LO input ports make it possible to cover all the major wireless infrastructure frequency bands using a single device. The IF outputs of the LTC5594 are designed to interface directly with most common A/D converter input interfaces. The high OIP3 and high conversion gain of the device eliminate the need for additional amplifiers in the IF signal path.APPLICATIONS 5G Base Station Front-haul/Back-haul Receivers Military and Satellite Receivers Point-to-Point Broadband Radios High Linearity Direct Conversion I/Q SDR Test Instrumentation DPD Receivers

The LTC7812 is a high performance synchronous Boost+Buck DC/DC switching regulator controller that drives all N-channel power MOSFET stages. It contains independent step-up (boost) and step-down (buck) controllers that can regulate two separate outputs or be cascaded to regulate an output voltage from an input voltage that can be above, below or equal to the output voltage. The LTC7812 operates from a wide 4.5V to 38V input supply range. When biased from the output of the boost regulator, the LTC7812 can operate from an input supply as low as 2.5V after start-up. The 33?A no-load quiescent current extends operating run time in battery-powered systems.Unlike conventional buck-boost regulators, the LTC7812?s cascaded Boost+Buck solution has continuous, nonpulsating, input and output currents, substantially reducing voltage ripple and EMI. The LTC7812 has independent feedback and compensation points for the boost and buck regulation loops, enabling a fast output transient response that can be easily optimized externally.Applications Automotive and Industrial Power Systems High Power Battery Operated Systems

DC1049A: Demo Board for the LTC4264 High Power PD Interface Controller with 750mA Current Limit.

Demonstration circuit DC1154 is a Telecom non isolated DC/DC converter featuring the LTC3873 constant frequency current mode flyback controller. The DC1154 converts 36V to 72V input voltage to an isolated 3A of output current at 3.3V. The 200kHz constant frequency operation is maintained down to very light load to reduce low frequency noise generated over a wide range of load current. The DC1154 also provides an isolated design by installing the optocoupler and LTC4430 related circuitry. The demonstration circuit can be easily modified to generate different output voltages up to 15V. As output voltage is increased, the maximum output current must be reduced to limit the output power to no more than 10W.

The AD8306 is a complete IF limiting amplifier, providing bothan accurate logarithmic (decibel) measure of the input signal(the RSSI function) over a dynamic range of 100 dB, and aprogrammable limiter output, useful from 5 MHz to 400 MHz.An evaluation board is available for this product and may be ordered using the following product number: AD8306-EVAL. Schematic and layout for this evaluation board is contained in the product datasheet.

The HMC8073 is a 6-bit digital step attenuator (DSA), operating from 0.6 GHz to 3.0 GHz, that features 31.5 dB of attenuation range with 0.5 dB steps.The HMC8073 is implemented in a silicon process, offering a fast settling time, low power consumption, and high electrostatic discharge (ESD) robustness. The device features safe state transitions, allowing attenuation state changes without overshooting, and is optimized for excellent step accuracy and high power and high linearity over frequency and temperature range. The radio frequency (RF) input and output are internally matched to 50 ? and do not require any external matching components. The design is bidirectional, and the RF input and output are interchangeable.The external address feature of the HMC8073 allows users to control up to eight DSAs using a single bus. The DSA has an on-chip regulator that supports a wide supply operating range from 3.3 V to 5.0 V with no performance change in electrical characteristics. The HMC8073 incorporates a complementary metal-oxide semiconductor (CMOS)- and transistor transitory logic (TTL)- compatible interface that supports serial (3-wire) control of the attenuator.The HMC8073 comes in an RoHS compliant, compact, 3 mm ? 3 mm LFCSP package.Applications Cellular infrastructure Microwave radios? Very small aperture terminals Test equipment and sensors

DC1090A: Demo Board for LTC2954 Push Button On/Off Controller with µP Interrupt

The LTC2323-12 is a low noise, high speed dual 12-bit + sign successive approximation register (SAR) ADC with differential inputs and wide input common mode range. Operating from a single 3.3V or 5V supply, the LTC2323-12 has an 8VP-P differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. The LTC2323-12 achieves ?0.5LSB INL typical, no missing codes at 12 bits and 73dB SNR.The LTC2323-12 has an on-board low drift (20ppm/?C max) 2.048V or 4.096V temperature-compensated reference. The LTC2323-12 also has a high speed SPI-compatible serial interface that supports CMOS or LVDS. The fast 5Msps per channel throughput with one-cycle latency makes the LTC2323-12 ideally suited for a wide variety of high speed applications. The LTC2323-12 dissipates only 38mW per channel and offers nap and sleep modes to reduce the power consumption to 5?W for further power savings during inactive periods. Bits LTC2323-12 12 LTC2323-14 14 LTC2323-16 16 Applications High Speed Data Acquisition Systems Communications Remote Data Acquisition Imaging Optical Networking Automotive Multiphase Motor Control

DC661A-A: Demo Board for the LT3468 Photoflash Capacitor Chargers in ThinSOT.

The AD9094 is an 8-bit, 1 GSPS, quad analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed to sample wide bandwidth analog signals up to 1.4 GHz. The AD9094 is optimized for wide input bandwidth, a high sampling rate, high works linearity, and low power in a small package. The quad-ADC cores feature multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs that support a variety of user-selectable input ranges. An integrated voltage reference facilitates design considerations. The analog inputs and clock signals are differential inputs. Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of JESD204B Subclass 1 or Subclass 0, high speed, serialized outputs, depending on the sample rate and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, SYNCINB?AB, and SYNCINB?CD input pins. The AD9094 has flexible power-down options that allow significant power savings when desired. To program the power down options, use the 1.8 V capable, serial port interface (SPI). The AD9094 is available in a Pb-free, 72-lead, lead frame chip scale package (LFCSP) and is specified over a junction temperature range of ?40?C to +105?C. This product may be protected by one or more U.S. or international patents. Note that throughout the data sheet, multifunction pins, such as PDWN/STBY, are referred to either by the entire pin name or by a single function of the pin, for example, PDWN, when only that function is relevant. PRODUCT HIGHLIGHTS Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide, full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.APPLICATIONSLaser imaging, detection, and ranging (LIDAR)CommunicationsDigital oscilloscope (DSO)Ultrawideband satellite receiversInstrumentation