The AD8344 is a high performance, broadband active mixer. It is well suited for demanding receive-channel applications thatrequire wide bandwidth on all ports and very low intermodulation distortion and noise figure.The AD8344 provides a typical conversion gain of 4.5 dB at 890 MHz. The integrated LO driver supports a 50 ? inputimpedance with a low LO drive level, helping to minimize external component count.The single-ended 50 ? broadband RF port allows for easy interfacing to both active devices and passive filters. The RFinput accepts input signals as large as 1.7 V p-p or 8.5 dBm (re: 50 ?) at P1dB.The open-collector differential outputs provide excellent balance and can be used with a differential filter or IF amplifier,such as the AD8369 or AD8351. These outputs may also be converted to a single-ended signal through the use of a matchingnetwork or a transformer (balun).When centered on the VPOS supply voltage, each of the differential outputs may swing2.5 V p-p.The AD8344 is fabricated on an Analog Devices proprietary, high performance SiGe IC process. The AD8344 is availablein a 16-lead LFCSP package. It operates over a ?40?C to +85?C temperature range.An evaluation board is also available.ApplicationsCellular base station receiversISM receiversRadio linksRF Instrumentation

The AD8362 is a true rms-responding power detector that has a 65 dB measurement range. It is intended for use in a variety of high frequency communication systems and in instrumentation requiring an accurate response to signal power. It is easy to use, requiring only a single supply of 5 V and a few capacitors. It operates from arbitrarily low frequencies to over 3.8 GHz and accepts inputs from ?52 dBm to +8 dBm with crest factors that are typical of quadrature amplitude modulation (QAM) and orthogonal frequency division multiplexing (OFDM) modulation schemes.The input signal is applied to a resistive ladder attenuator that comprises the input stage of a variable gain amplifier (VGA). The 12 tap points are smoothly interpolated using a proprietary technique to provide a continuously variable attenuator, which is controlled by a voltage applied to the VSET pin. The resulting signal is applied to a high performance broadband amplifier. Its output is measured by an accurate square-law detector cell. The fluctuating output is then filtered and compared with the output of an identical squarer, whose input is a fixed dc voltage applied to the VTGT pin, usually the accurate reference of 1.25 V pro-vided at the VREF pin.The difference in the outputs of these squaring cells is integrated in a high gain error amplifier, generating a voltage at the VOUT pin with rail-to-rail capabilities. In a controller mode, this low noise output can be used to vary the gain of a host system?s RF amplifier, thus balancing the setpoint against the input power. Optionally, the voltage at VSET can be a replica of the RF signal?s amplitude modulation, in which case the overall effect is to remove the modulation component prior to detection and low-pass filtering. The corner frequency of the averaging filter can be lowered without limit by adding an external capacitor at the CLPF pin. The AD8362 can be used to determine the true power of a high frequency signal having a complex low frequency modulation envelope, or simply as a low frequency rms volt-meter. The high-pass corner generated by its offset-nulling loop can be lowered by a capacitor added on the CHPF pin.Used as a power measurement device, VOUT is strapped to VSET. The output is then proportional to the logarithm of the rms value of the input. In other words, the reading is presented directly in decibels and is conveniently scaled 1 V per decade, or 50 mV/dB; other slopes are easily arranged. In controller modes, the voltage applied to VSET determines the power level required at the input to null the deviation from the setpoint. The output buffer can provide high load currents.The AD8362 has 1.3 mW power consumption when powered down by a logic high applied to the PWDN pin. It powers up within about 20 ?s to its nominal operating current of 20 mA at 25?C. The AD8362 is supplied in a 16-lead TSSOP for operation over the temperature range of ?40?C to +85?C.ApplicationsPower amplifier linearization/control loops Transmitter power controls Transmitter signal strength indication (TSSI) RF instrumentation

The AD8366 is a matched pair of fully differential, low noise and low distortion, digitally programmable variable gain amplifiers (VGAs). The gain of each amplifier can be programmed separately or simultaneously over a range of 4.5 dB to 20.25 dB in steps of 0.25 dB. The amplifier offers flat frequency performance from dc to 70 MHz, independent of gain code.The AD8366 offers excellent spurious-free dynamic range, suitable for driving high resolution analog-to-digital converters (ADCs). The NF at maximum gain is 11.4 dB at 10 MHz and increases ~2 dB for every 4 dB decrease in gain. Over the entire gain range, the HD3/HD2 are better than ?90 dBc for 2 V p-p at the output at 10 MHz into 200 ?. The two-tone intermodulation distortion of ?90 dBc into 200 ? translates to an OIP3 of 45 dBm (38 dBVrms). The differential input impedance of 200 ? provides a well-defined termination. The differential output has a low impedance of ~25 ?.The output common-mode voltage defaults to VPOS/2 but can be programmed via the VCMA and VCMB pins over a range of voltages. The input common-mode voltage also defaults to VPOS/2 but can be driven down to 1.5 V. A built-in, dc offset compensation loop can be used to eliminate dc offsets from prior stages in the signal chain. This loop can also be disabled if dc-coupled operation is desired.The digital interface allows for parallel or serial mode gain programming. The AD8366 operates from a 4.75 V to 5.25 V supply and consumes typically 180 mA. When disabled, the part consumes roughly 3 mA. The AD8366 is fabricated using Analog Devices, Inc., advanced silicon-germanium bipolar process, and it is available in a 32-lead exposed paddle LFCSP package. Performance is specified over the ?40?C to +85?C temperature range.ApplicationsBaseband I/Q receiversDiversity receiversWideband ADC drivers?

The AD8452-EVALZ is a platform for the AD8452, designed for investigation of the AD8452 analog and pulse-width modulation (PWM) features and performance without the added complications of a driver and/or switch mode power supply (SMPS) design. For convenience, a precision 5 V reference IC and four trim pots are built in to the evaluation board, for driving the battery current and voltage ISET and VSET inputs. All device pins are accessible with test loops or probe landings. At the same time, the AD8452-EVALZ has the flexibility to interface and drive a typical half bridge inductor input SMPS with output levels in the 1 A to 15 A range. SMPS and associated components are specified and sourced by the user. The AD8452 is intended for use as the core controller for commercial battery test and formation systems. Its advanced miniaturization and extraordinarily high level of analog precision meet the challenge of mass production of high energy density storage lithium ion packs for transportation and energy storage in homes. When working with the evaluation board, consult the AD8452 data sheet for a detailed device Theory of Operation and for additional information in conjunction with user guide UG-1180.

The AD9148 is a quad, 16-bit, high dynamic range, digital-toanalogconverter (DAC) that provides a sample rate of 1000 MSPS.These devices include features optimized for direct conversiontransmit applications, including gain, phase, and offset compensation.The DAC outputs are optimized to interface seamlessly withanalog quadrature modulators such as the?ADL5371/ADL5372/ADL5373/ADL5374/ADL5375/. A serial peripheral interface (SPI)is provided for programming of the internal device parameters.Full-scale output current can be programmed over a range of 10 mAto 30 mA. The devices operate from 1.8 V and 3.3 V supplies fora total power consumption of 3 W at the maximum sample rate.They are enclosed in 196-ball chip scale package ball grid arraywith the option of an attached heat spreader..Product Highlights1. Low noise and inter-modulation distortion (IMD) enable highquality synthesis of wideband signals from baseband to highintermediate frequencies.2. A proprietary DAC output switching technique enhancesdynamic performance.3. The current outputs are easily configured for various singleendedor differential circuit topologies.4. LVDS data input interface includes FIFO to ease input timing.Applications Wireless infrastructure LTE, TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM MIMO/Transmit diversity Digital high or low IF synthesis

The AD9173 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8-lane, 15.4 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.The AD9173 features three complex data input channels per RF DAC that are bypassable. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The device supports up to a 1.54 GSPS complex data rate per input channel and is capable of aggregating multiple complex input data streams up to a maximum complex data rate of 1.54 GSPS. Additionally, the AD9173 supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3.08 GSPS (with 11-bit resolution using 16-bit serializer/deserializer (SERDES) packing) and 3.4 GSPS (with 11-bit resolution using 12-bit SERDES packing).The AD9173 is available in a 144-ball BGA_ED package.APPLICATIONS Wireless communications infrastructure Multiband base station radios Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE)PRODUCT HIGHLIGHTS Supports single-band and multiband wireless applications with three bypassable complex data input channels per RF DAC at a maximum complex input data rate of 1.54 GSPS with 11-bit resolution and 1.23 GSPS with 16-bit resolution. One independent NCO per input channel. Ultrawide bandwidth channel bypass modes supporting up to 3.08 GSPS data rates with 11-bit resolution, 16-bit SERDES packing and 3.4 GSPS with 11-bit resolution, 12-bit SERDES packing. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.

The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The ?3 dB bandwidth of the ADC input is 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage referenceeases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signalprocessing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimationfilters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9208 has several functions that simplify the automatic gain control (AGC) function in acommunications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoidan overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9208 has flexible power-down options that allow significant power savings when desired. All of these features canbe programmed using a 3-wire serial port interface (SPI).The AD9208 is available in a Pb-free, 196-ball BGA, specified over the ?40?C to +85?C ambient temperature range. Thisproduct is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input ?3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers. Fast NCO switching enabled through GPIO pins. A SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature dioide for system thermal management. 12mm ? 12mm 196-Lead BGAApplications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital con-verter (ADC) with an on-chip sample-and-hold circuit designedfor low cost, low power, small size, and ease of use. The productoperates at a conversion rate of up to 65 MSPS and is optimized foroutstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock for theappropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximizeflexibility and minimize system cost, such as programmableclock and data alignment and programmable digital test patterngeneration. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI).The AD9219 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of ?40?C to +85?C.Product Highlights Small Footprint. Four ADCs are contained in a small, space-saving package. Low power of 94 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9228 (12-bit), and AD9259 (14-bit). ApplicationsMedical imaging and nondestructive ultrasoundPortable ultrasound and digital beam-forming systemsQuadrature radio receiversDiversity radio receiversTape drivesOptical networkingTest equipment

The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block. The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver.?The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9234 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.The AD9234 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.Product Highlights Low power consumption analog core, 12-bit, 1.0 GSPS dual analog-to-digital converter (ADC) with 1.5 W per channel. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm 64-lead LFCSP. Pin compatible with the AD9680 14-bit, 1 GSPS dual ADC.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point-to-point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9257 is an octal, 14-bit, 40 MSPS and 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9257 is available in an RoHS-compliant, 64-lead LFCSP. It is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent. APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Optical networking Test EquipmentPRODUCT HIGHLIGHTS Small Footprint. Eight ADCs are contained in a small, space-saving package. Low Power of 55 mW/Channel at 65 MSPS with Scalable Power Options. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 455 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin Compatible with the AD9637 (12-Bit Octal ADC).