The ADuC7124?is a fully integrated, 1 MSPS, 12-bit data acquisition system incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip.The ADC consists of up to 12 single-ended inputs. An additional two inputs are available but are multiplexed with the two DAC output pins. The ADC can operate in single-ended or differential input mode. The ADC input voltage range is 0 V to VREF. A low drift band gap reference, temperature sensor, and voltage comparator complete the ADC peripheral set.The DAC output range is programmable to one of three voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence.The device operates from an on-chip oscillator and a PLL generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI?, 16-bit/32-bit RISC machine, which offers up to 41 MIPS of peak performance. Thirty-two kilobytes of SRAM and 126 kB of nonvolatile Flash/EE memory are provided on-chip. The ARM7TDMI core views all memory and registers as a single linear array.The ADuC7124 contains an advanced interrupt controller. The vectored interrupt controller (VIC) allows every interrupt to be assigned a priority level. It also supports nested interrupts to a maximum level of eight per IRQ and FIQ. When IRQ and FIQ interrupt sources are combined, a total of 16 nested interrupt levels are supported.On-chip factory firmware supports in-circuit download via the UART serial interface port or the I2C port, while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart? development system supporting this MicroConverter? family.The part contains a 16-bit PWM with six output signals.For communication purposes, the part contains 2? I2C channels that can be individually configured for master or slave mode. An SPI interface supporting both master and slave modes is also provided. Thirdly, 2? UART channels are provided. Each UART contains a configurable 16-bit FIFO with receive and transmit buffers.The part operates from 2.7 V to 3.6 V and is specified over an industrial temperature range of ?40?C to +125?C. When operating at 41.78 MHz, the power dissipation is typically 120 mW. The ADuC7124 is available in a 64-lead LFCSP package.APPLICATIONS Industrial control and automation systems Smart sensors, precision instrumentation Base station systems, optical networking Patient monitoring

The AD5930 is a waveform generator with programmable frequency sweep and output burst capability. Utilizing embedded digital processing that allows enhanced frequency control, the device generates synthesized analog or digital frequency-stepped waveforms. Because frequency profiles are preprogrammed, continuous write cycles are eliminated and thereby free up valuable DSP/microcontroller resources. Waveforms start from a known phase and are incremented phase continuously, which allows phase shifts to be easily determined. Consuming only 8 mA, the AD5930 provides a convenient low power solution to waveform generation.The AD5930 can be operated in a variety of modes. In continuous output mode, the device outputs the required frequency for a defined length of time and then steps to the next frequency. The length of time the device outputs a particular frequency is either preprogrammed and the device increments the frequency automatically, or, alternatively, is incremented externally via the CTRL pin. In burst mode, the device outputs its frequency for a length of time and then returns to midscale for a further predefined length of time before stepping to the next frequency. When the MSBOUT pin is enabled, a digital output is generated.To program the device, the user enters the start frequency, the increment step size, the number of increments to be made, and the time interval that the part outputs each frequency. The frequency sweep profile is initiated, started, and executed by toggling the CTRL pin.A number of different sweep profiles are offered. Frequencies can be stepped in triangular-sweep mode, which continuously sweeps up and down through the frequency range. Alternatively, in saw-sweep mode, the frequency is swept up through the frequency range, but returns to the initial frequency before executing the sweep again. In addition, a single frequency or burst can be generated without any sweep.The AD5930 is written to via a 3-wire serial interface, which operates at clock rates up to 40 MHz. The device operates with a power supply from 2.3 V to 5.5 V. Note that AVDD and DVDD are independent of each other and can be operated from different voltages. The AD5930 also has a standby function, which allows sections of the device that are not being used to be powered down.The AD5930 is available in a 20-lead pb-free TSSOP package.Applications Frequency sweeping/radar Network/impedance measurements Incremental frequency stimulus Sensory applications Proximity and motion BFSK Frequency bursting/pulse trains

BUF16821 Evaluation Module USB

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Dual Brushed DC Motor BoosterPack featuring DRV8848

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

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Evaluation Module for TPS61256; Tiny Boost Converter with Input Current Limit and Bypas

Demonstration circuit 1050 is a monolithic step-down DC/DC switching regulator featuring the LT3503. The demo board is designed for a 3.3V/1.2A output from a 4.5V to 20V input. The 2.2MHz switching frequency allows the use of small, low cost external components and results in a low, predictable output ripple.