The LT3574 is a monolithic switching regulator specifically designed for the isolated flyback topology. No third winding or opto-isolator is required for regulation. The part senses the isolated output voltage directly from the primary side flyback waveform. A 0.65A, 60V NPN power switch is integrated along with all control logic into a 16?lead MSOP package. The LT3574 operates with input supply voltages from 3V to 40V, and can deliver output power up to 3W with no external power switch. The LT3574 utilizes boundary mode operation to provide a small magnetic solution with improved load regulation. The output voltage is easily set with two external resistors and the transformer turns ratio. Off-the-shelf transformers are available for many applications.Applications Industrial, Automotive and Medical Isolated Power Supplies

Demonstration circuit 2069A features LT8490, a high performance buck-boost converter that implements an MPPT function and flexible charging profiles suitable for most battery types such as flooded and sealed lead acid batteries and Lithium-Ion batteries, and can operate from input voltages above, below or equal to the battery voltage.

Demonstration circuit 2234A is a synchronous sepic converter featuring the LT8711 multitopology switching controller. The LT8711 is a current mode PWM DC/DC controller with a dual input LDO to optimize gate driver efficiency. Ultralow 15μA quiescent current in low noise Burst Mode® operation achieves high efficiency at very light loads and helps extend the run-time in battery powered applications when in standby mode. The LT8711 switching frequency can be programmed either via oscillator resistor or external clock over a 100kHz to 750kHz range.

Demonstration circuit 2910A is low VIN, high efficiency, and dual 2A output µModule DC/DC converter. The board operates by default at a fixed 2MHz and can be synchronized from 1MHz to 3MHz via the MODE/SYNC pin. With its high switching frequency and current mode architecture, a fast transient response to line and load changes is possible without sacrificing stability. The DC2910A can be used in forced continuous mode or pulse skip mode for low noise, or in burst mode operation for high efficiency at light loads. The demo board features the LTM4691, which is available in a low profile 3mm x 4mm x 1.2mm LGA package. Please see the LTM4691 datasheet for more detailed information. It is recommended to read the data sheet for the LTM4691 prior to making any changes to the DC2910A.

The AD7682/AD7689 are 4-channel/8-channel, 16-bit, chargeredistribution successive approximation register (SAR) analog-to-digitalconverters (ADCs) that operate from a single powersupply, VDD.The AD7682/AD7689 contain all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; a 4-channel (AD7682) or 8-channel (AD7689) low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.The AD7682/AD7689 use a simple serial port interface (SPI) for?writing to the configuration register and receiving conversion?results. The SPI interface uses a separate supply, VIO, which is set?to the host logic level. Power dissipation scales with throughput.The AD7682/AD7689 are housed in a tiny 20-lead lead frame?chip scale package (LFCSP) and 20-lead wafer level chip scale?package (WLCSP) with operation specified from ?40?C to?+85?C. The AD7689 includes an extended temperature range?model with specifications guaranteed to a maximum?temperature (TMAX) of +125?C.Applications Multichannel system monitoring Battery-powered equipment Medical instruments: ECG/EKG Mobile communications: GPS Power line monitoring Data acquisition Seismic data acquisition systems Instrumentation Process control

The ADAU1452 /?ADAU1451?/?ADAU1450 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP? devices. The restructured hardware architecture is optimized for efficient audio processing. The audio processing algorithms are realized in sample-by-sample and block-by-block paradigms that can both be executed simultaneously in a signal processing flow created using the graphical programming tool, SigmaStudio?. The restructured digital signal processor (DSP) core architecture enables some types of audio processing algorithms to be executed using significantly fewer instructions than were required on previous SigmaDSP generations, leading to vastly improved code efficiency.The 1.2 V, 32-bit DSP core can run at frequencies of up to 294.912 MHz and execute up to 6144 instructions per sample at the standard sample rate of 48 kHz. However, in addition to industry-standard rates, a wide range of sample rates are available. The integer PLL and flexible clock generator hardware can generate up to 15 audio sample rates simultaneously. These clock generators, along with the on-board asynchronous sample rate converters (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1452 / ADAU1451 / ADAU1450 ideal audio hubs that greatly simplify the design of complex multirate audio systems.The ADAU1452 / ADAU1451 / ADAU1450 interface with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry, due to their highly configurable serial ports, S/PDIF interfaces (on the ADAU1452 and ADAU1451), and multipurpose input/output pins. The devices can also directly interface with pulse density modulation (PDM) output microelectromechanical (MEMS) microphones, due to integrated decimation filters specifically designed for that purpose.Independent slave and master I2C/serial peripheral interface (SPI) control ports allow the ADAU1452 / ADAU1451 / ADAU1450 not only to be programmed and configured by an external master device, but also to act as masters that can program and configure external slave devices directly. This flexibility, combined with self boot functionality, enables the design of standalone systems that do not require any external input to operate.The power efficient DSP core executes full programs, consumes only a few hundred milliwatts (mW) of power, and can run at a maximum program load while consuming less than a watt, even in worst case temperatures exceeding 100?C. This relatively low power consumption and small footprint make the ADAU1452 / ADAU1451 / ADAU1450 ideal replacements for large, general-purpose DSPs that consume more power at the same processing load.Differences between the ADAU1452, ADAU1451, and ADAU1450The five variants of this device are differentiated by memory, DSP core frequency, availability of S/PDIF interfaces, ASRC configuration, and temperature range.Because the ADAU1450 does not contain an S/PDIF receiver or transmitter, the SPDIFIN and SPDIFOUT pins are nonfunctional. Additionally, the settings of any registers related to the S/PDIF input or output in the ADAU1450 do not have any effect on the operation of the device.Because the ADAU1450 does not contain ASRCs, the settings of any registers related to the ASRCs in the ADAU1450 do not have any effect on the operation of the device.APPLICATIONS Automotive audio processing Head units Navigation systems Rear seat entertainment systems DSP amplifiers (sound system amplifiers) Commercial and professional audio processing Consumer audio processing

The ADAU7002 converts a stereo PDM bit stream into a PCMoutput. The source for the PDM data can be two microphonesor other PDM sources. The PCM audio data is output on aserial audio interface port in either I2S or TDM format.The ADAU7002 is specified over the commercial temperaturerange (?40?C to +85?C). It is available in a halide-free, 8-ball,1.56 mm ? 0.76 mm, wafer level chip scale package (WLCSP).Applications Mobile computing Portable electronics Consumer electronics

The ADF7021 is a low power, highly integrated 2FSK/3FSK/4FSK transceiver. It is designed to operate in the narrowband, license-free ISM bands and licensed bands in the 80 MHz to 650 MHz and 862 MHz to 940 MHz frequency ranges. It has both Gaussian and raised cosine data filtering options to improve spectral efficiency for narrowband applications.It is suitable for circuit applications targeted at European ETSI-EN 300-220, the Japanese ARIB STD-T67, the Chinese Short Range Device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021 very suitable for price-sensitive and area-sensitive applications.The transmit section contains a voltage controlled oscillator (VCO) and a low noise fractional-N PLL with output resolution of <1 ppm. This frequency-agile PLL allows the ADF7021 to be used in frequency hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from ?16 dBm to +13 dBm and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.A low IF architecture is used in the receiver (100 kHz), minimizing power consumption and the external component count while avoiding interference problems at low frequencies. The IF filter has programmable bandwidths of 12.5 kHz, 18.75 kHz, and 25 kHz. The ADF7021 supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range, allowing the PLL to track out the frequency error in the incoming signal.An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, and the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full operating temperature range of ?40?C to +85?C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.

The ADF7024 is an ultralow power, integrated transceiver for use in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. Its ease of use and high performance make it suitable for a wide variety of wireless applications. The ADF7024 is suitable for operation under the European ETSI EN 300-220 regulation, the North American FCC Part 15 regulation, and other similar regulatory standards.The ADF7024 can operate under a number of predefined radio profiles. For each radio profile, optimized register settings are provided for the ADF7024 radio. This ensures that the RF communication layer works seamlessly, allowing the user to concentrate on the protocol and system level design and prototyping. The radio profiles cover common data rate and modulation options. There are six radio profiles in total, as shown in Table 1.The ADF7024 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance.The low IF receiver minimizes power consumption and provides excellent sensitivity. The receiver is exceptionally linear and, therefore, is very resilient to the presence of interferers in spectrally noisy environments. The highly efficient transmitter has programmable output power up to 13.5 dBm and automatic power amplifier (PA) ramping to meet transient spurious specifications. The RF synthesizer comprises a voltage controlled oscillator (VCO), a low noise fractional-N phase-locked loop (PLL) and a loop filter, all of which are fully integrated and automatically calibrated. This agile frequency synthesizer facilitates the implementation of frequency-hopping spread spectrum (FHSS) systems.The smart wake mode (SWM) allows the ADF7024 to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption.The ADF7024 eases the processing burden of the host processor by integrating the lower layers of a typical communication protocol stack. The host processor can configure the ADF7024 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller).For more information, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package.APPLICATIONS Wireless sensor networks (WSNs) Home and building automation Asset tracking Process and building control Industrial control Internet of Things (IoT)

The ADL5391 draws on three decades of experience in advanced analog multiplier products. It provides the same general mathematical function that has been field proven to provide an exceptional degree of versatility in function synthesis:VW?= ? ? (VX?x VY)/1 V + VZThe most significant advance in the ADL5391 is the use of anew multiplier core architecture, which differs markedly fromthe conventional form that has been in use since 1970. Theconventional structure that employs a current mode, translinearcore is fundamentally asymmetric with respect to the X and Yinputs, leading to relative amplitude and timing misalignmentsthat are problematic at high frequencies. The new multiplier coreeliminates these misalignments by offering symmetric signalpaths for both X and Y inputs. The Z input allows a signal to beadded directly to the output. This can be used to cancel a carrieror to apply a static offset voltage.The fully differential X, Y, and Z input interfaces are operationalover a ?2 V range, and they can be used in single-ended fashion.The user can apply a common mode at these inputs to varyfrom the internally set VPOS/2 down to ground. If these inputsare ac-coupled, their nominal voltage will be VPOS/2. These inputinterfaces each present a differential 500 ? input impedance up toapproximately 700 MHz, decreasing to 50 ? at 2 GHz. The gainscaling input, GADJ, can be used for fine adjustment of the gainscaling constant (?) about unity.The differential output can swing ?2 V about the VPOS/2common-mode and can be taken in a single-ended fashion aswell. The output common mode is designed to interface directlyto the inputs of another ADL5391. Light dc loads can be groundreferenced; however, ac-coupling of the outputs is recommendedfor heavy loads.The ENBL pin allows the ADL5391 to be disabled quickly to astandby mode. It operates off supply voltages from 4.5 V to 5.5 Vwhile consuming approximately 130 mA.The ADL5391 is fabricated on Analog Devices, Inc. proprietary,high performance, 65 GHz, SOI complementary, SiGe bipolarIC process. It is available in a 16-lead, RoHS compliant, LFCSPand operates over a ?40?C to +85?C temperature range.Evaluation boards are available.Applications Wideband multiplication and summing High frequency analog modulation Adaptive antennas (diversity/phased array) Square-law detectors and true rms detectors Accurate polynomial function synthesis DC capable VGA with very fast control