The HMC504LC4B is a GaAs MMIC Low NoiseWideband Amplifier housed in a leadless 4?4 mm ceramicsurface mount package. The amplifier operatesbetween 14 and 27 GHz, providing up to 19 dB ofsmall signal gain, 2.2 dB noise figure, and output IP3of +26 dBm, while requiring only 90 mA from a +4Vsupply. The P1dB output power of up to +17 dBmenables the LNA to function as a LO driver for balanced,I/Q or image reject mixers. The HMC504LC4Balso features I/Os that are DC blocked and internallymatched to 50 ?, making it ideal for high capacitymicrowave radios or VSAT applications. This versatileLNA is also available in die form as the HMC-ALH476.APPLICATIONSThis HMC504LC4B is ideal for: Point-to-Point Radios Point-to-Multi-Point Radios Military & Space Test Instrumentation

The HMC753 is a GaAs MMIC Low Noise Wideband Amplifier housed in a leadless 4x4 mm plastic surface mount package. The amplifier operates between 1 and 11 GHz, providing up to 16.5 dB of small signal gain, 1.5 dB noise figure, and output IP3 of +30 dBm, while requiring only 55 mA from a +5V supply. The P1dB output power of up to +18 dBm enables the LNA to function as a LO driver for balanced, I/Q or image reject mixers. The HMC753 also features I/Os that are DC blocked and internally matched to 50 Ohms, making it ideal for high capacity microwave radios or VSAT applications. This versatile LNA is also available in die form as the?HMC-ALH444.Applications Point-to-Point Radios Point-to-Multi-Point Radios Military & Space Test Instrumentation.

The HMC859LC3 is a Divide-by-8 with Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications. The HMC859LC3 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All input signals to the HMC859LC3 are terminated with 50 ? to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50 ? terminated system, while DC blocking capacitors may be used if the terminating system is 50 ? to a non-ground DC voltage. The HMC859LC3 operates from a single -3.3 V DC supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS High Speed Frequency Divider?(up to 26 GHz) Clock Synthesis Phase Locked Loops Broadband Test & Measurement

The HMC741 is an InGaP Heterojunction Bipolar Transistor (HBT) Gain Block MMIC SMT amplifier covering 0.05 to 3 GHz. Packaged in an industry standard SOT89, the amplifier can be used as a cascadable 50 Ohm RF or IF gain stage as well as a PA or LO driver with up to +18.5 dBm output power. The HMC741 offers 20 dB of gain with a +42 dBm output IP3 at 200 MHz, and can operate directly from a +5V supply. The HMC741 exhibits excellent gain and output power stability over temperature, while requiring a minimal number of external bias components.Applications Cellular/3G & WiMAX/4G Fixed Wireless & WLAN CATV, Cable Modem & DBS Microwave Radio & Test Equipment IF & RF Applications

RF Amplifier 10 GHz gain block, Linr Drive/Gain Block

Phase Locked Loops - PLL WBand RF PLL VCO, 25-3000MHz

Demonstration circuit SCP-LT8362-S-EVALZ features the LT8362 in a SEPIC configuration. It operates with a switching frequency of 2MHz and has an output voltage of 12V. Like all boards in the Signal Chain Power series, this board is designed to be easily plugged into other SCP boards to form a complete signal chain power system, enabling fast evaluation of low power signal chains. To evaluate this board, some universal SCP hardware is required, namely: SCP-INPUT-EVALZ SCP-OUTPUT-EVALZ SCP-FILTER-EVALZ SCP-THRUBRD-EVALZ SCP-1X2BKOUT-EVALZ SCP-1X5BKOUT-EVALZ SCP-5X1-EVALZ   To properly evaluate SCP series demo boards, you will need the SCP Configurator companion software. SCP Configurator can help you choose the right board and topology for your design. Note that the Demo Manual does not cover details important to the operation and configuration regarding the LT8362. Please refer to the LT8362 datasheet for a complete description of the part.

The SSM2604 is a low power, high quality stereo audio codec for portable digital audio applications with one set of stereo programmable gain amplifier (PGA) line inputs. It features two 24-bit analog-to-digital converter (ADC) channels and two 24-bit digital-to-analog (DAC) converter channels.The SSM2604 can operate as a master or a slave. It supports various master clock frequencies, including 12 MHz or 24 MHz for USB devices; standard 256 fS or 384 fS based rates, such as 12.288 MHz and 24.576 MHz; and many common audio sampling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.The SSM2604 can operate at power supplies as low as 1.8 V for the analog circuitry and as low as 1.5 V for the digital circuitry. The maximum voltage supply is 3.6 V for all supplies.The SSM2604 is specified over the industrial temperature range of ?40?C to +85?C. It is available in a 20-lead, 4 mm ? 4 mm lead frame chip scale package (LFCSP).APPLICATIONS Mobile phones MP3 players Portable gaming Portable electronics Educational toys

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.