The ADAU1372 is a codec with four inputs and two outputs, which incorporates asynchronous sample rate converters. Optimized for low latency and low power, the ADAU1372 is ideal for headsets, handsets, and headphones. The ADAU1372 has built-in programmable gain amplifiers (PGAs); thus, with the addition of just a few passive components and a crystal, the ADAU1372 provides a solution for headset audio needs. Microphone preamplifiers, ADCs, DACs, headphone amplifiers and serial ports for connections to an external DSP.APPLICATIONS Handsets, headsets, and headphones Bluetooth handsets, headsets, and headphones Personal navigation devices Digital still and video cameras

The ADAU1452 /?ADAU1451?/?ADAU1450 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP? devices. The restructured hardware architecture is optimized for efficient audio processing. The audio processing algorithms are realized in sample-by-sample and block-by-block paradigms that can both be executed simultaneously in a signal processing flow created using the graphical programming tool, SigmaStudio?. The restructured digital signal processor (DSP) core architecture enables some types of audio processing algorithms to be executed using significantly fewer instructions than were required on previous SigmaDSP generations, leading to vastly improved code efficiency.The 1.2 V, 32-bit DSP core can run at frequencies of up to 294.912 MHz and execute up to 6144 instructions per sample at the standard sample rate of 48 kHz. However, in addition to industry-standard rates, a wide range of sample rates are available. The integer PLL and flexible clock generator hardware can generate up to 15 audio sample rates simultaneously. These clock generators, along with the on-board asynchronous sample rate converters (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1452 / ADAU1451 / ADAU1450 ideal audio hubs that greatly simplify the design of complex multirate audio systems.The ADAU1452 / ADAU1451 / ADAU1450 interface with a wide range of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital audio devices, amplifiers, and control circuitry, due to their highly configurable serial ports, S/PDIF interfaces (on the ADAU1452 and ADAU1451), and multipurpose input/output pins. The devices can also directly interface with pulse density modulation (PDM) output microelectromechanical (MEMS) microphones, due to integrated decimation filters specifically designed for that purpose.Independent slave and master I2C/serial peripheral interface (SPI) control ports allow the ADAU1452 / ADAU1451 / ADAU1450 not only to be programmed and configured by an external master device, but also to act as masters that can program and configure external slave devices directly. This flexibility, combined with self boot functionality, enables the design of standalone systems that do not require any external input to operate.The power efficient DSP core executes full programs, consumes only a few hundred milliwatts (mW) of power, and can run at a maximum program load while consuming less than a watt, even in worst case temperatures exceeding 100?C. This relatively low power consumption and small footprint make the ADAU1452 / ADAU1451 / ADAU1450 ideal replacements for large, general-purpose DSPs that consume more power at the same processing load.Differences between the ADAU1452, ADAU1451, and ADAU1450The five variants of this device are differentiated by memory, DSP core frequency, availability of S/PDIF interfaces, ASRC configuration, and temperature range.Because the ADAU1450 does not contain an S/PDIF receiver or transmitter, the SPDIFIN and SPDIFOUT pins are nonfunctional. Additionally, the settings of any registers related to the S/PDIF input or output in the ADAU1450 do not have any effect on the operation of the device.Because the ADAU1450 does not contain ASRCs, the settings of any registers related to the ASRCs in the ADAU1450 do not have any effect on the operation of the device.APPLICATIONS Automotive audio processing Head units Navigation systems Rear seat entertainment systems DSP amplifiers (sound system amplifiers) Commercial and professional audio processing Consumer audio processing

The ADAU7002 converts a stereo PDM bit stream into a PCMoutput. The source for the PDM data can be two microphonesor other PDM sources. The PCM audio data is output on aserial audio interface port in either I2S or TDM format.The ADAU7002 is specified over the commercial temperaturerange (?40?C to +85?C). It is available in a halide-free, 8-ball,1.56 mm ? 0.76 mm, wafer level chip scale package (WLCSP).Applications Mobile computing Portable electronics Consumer electronics

The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltagecomparators fabricated on the Analog Devices, Inc. proprietaryXFCB3 Silicon Germanium (SiGe) bipolar process. TheADCMP580 features CML output drivers, the ADCMP581features reduced swing ECL (negative ECL) output drivers, andthe ADCMP582 features reduced swing PECL (positive ECL)output drivers.All three comparators offer 180 ps propagation delay and 100 psminimum pulse width for 10 Gbps operation with 200 fs randomjitter (RJ). Overdrive and slew rate dispersion are typically lessthan 15 ps.The ?5 V power supplies enable a wide ?2 V to +3 V inputrange with logic levels referenced to the CML/NECL/PECLoutputs. The inputs have 50 ? on-chip termination resistorswith the optional capability to be left open (on an individualpin basis) for applications requiring high impedance input. The CML output stage is designed to directly drive 400 mV into50 ? transmission lines terminated to ground. The NECL outputstages are designed to directly drive 400 mV into 50 ? terminatedto ?2 V. The PECL output stages are designed to directly drive400 mV into 50 ? terminated to VCCO ? 2 V. High speed latchand programmable hysteresis are also provided. The differentiallatch input controls are also 50 ? terminated to an independentVTT pin to interface to either CML or ECL or to PECL logic.The ADCMP580/ADCMP581/ADCMP582 are available in a16-lead LFCSP.Applications Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration

The EVAL-ADE1202EBZ is a full featured evaluation board, designed to allow the user to easily evaluate the ADE1202 dual-channel, configurable, isolated digital binary input IC performance in a context similar to a real binary input interface application. The evaluation kit requires purchasing the controller board for the system demonstration platform (EVAL-SDP-CB1Z). The evaluation kit includes evaluation software, written in LabVIEW®, which provides access to the registers and features of the device through a PC interface. Consult the ADE1202 data sheet in conjunction with this user guide when using the EVAL-ADE1202EBZ.

The ADF5002 prescaler is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input to a PLL IC, such as the ADF4156 or the ADF4106. The ADF5002 provides a divide-by-8 function. The ADF5002 operates from a 3.3 V supply and has differential 100 ? RF outputs to allow direct interface to the differential RF inputs of PLLs such as the ADF4156 and ADF4106.ApplicationsPLL frequency range extenderPoint-to-point radiosVSAT radiosCommunications test equipment

The ADF7021 is a low power, highly integrated 2FSK/3FSK/4FSK transceiver. It is designed to operate in the narrowband, license-free ISM bands and licensed bands in the 80 MHz to 650 MHz and 862 MHz to 940 MHz frequency ranges. It has both Gaussian and raised cosine data filtering options to improve spectral efficiency for narrowband applications.It is suitable for circuit applications targeted at European ETSI-EN 300-220, the Japanese ARIB STD-T67, the Chinese Short Range Device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021 very suitable for price-sensitive and area-sensitive applications.The transmit section contains a voltage controlled oscillator (VCO) and a low noise fractional-N PLL with output resolution of <1 ppm. This frequency-agile PLL allows the ADF7021 to be used in frequency hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from ?16 dBm to +13 dBm and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.A low IF architecture is used in the receiver (100 kHz), minimizing power consumption and the external component count while avoiding interference problems at low frequencies. The IF filter has programmable bandwidths of 12.5 kHz, 18.75 kHz, and 25 kHz. The ADF7021 supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range, allowing the PLL to track out the frequency error in the incoming signal.An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, and the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full operating temperature range of ?40?C to +85?C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.

The ADF7023-J is a very low power, high performance, highly integrated 2FSK/GFSK/MSK/GMSK transceiver designed for operation in the 902 MHz to 958 MHz frequency band, which covers the ARIB Standard T96 band at 950 MHz. Data rates from 1 kbps to 300 kbps are supported.The transmit RF synthesizer contains a VCO and a low noise fractional-N phase locked loop (PLL) with an output channel frequency resolution of 400 Hz. The VCO operates at twice the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from ?20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allow for Tx antenna diversity.The receiver is exceptionally linear, achieving an IP3 specification of ?12.2 dBm and ?11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at a ?2 MHz offset and 74 dB at a ?10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, AFC loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet. A patent pending image rejection calibration scheme is available by downloading the image rejection calibration firmware module to program RAM. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.See data sheet for additional information.Applications Smart metering IEEE 802.15.4g Home automation Process and building control Home Energy Management Systems (HEMS) Wireless sensor networks (WSNs) Wireless healthcare

The ADF7024 is an ultralow power, integrated transceiver for use in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. Its ease of use and high performance make it suitable for a wide variety of wireless applications. The ADF7024 is suitable for operation under the European ETSI EN 300-220 regulation, the North American FCC Part 15 regulation, and other similar regulatory standards.The ADF7024 can operate under a number of predefined radio profiles. For each radio profile, optimized register settings are provided for the ADF7024 radio. This ensures that the RF communication layer works seamlessly, allowing the user to concentrate on the protocol and system level design and prototyping. The radio profiles cover common data rate and modulation options. There are six radio profiles in total, as shown in Table 1.The ADF7024 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance.The low IF receiver minimizes power consumption and provides excellent sensitivity. The receiver is exceptionally linear and, therefore, is very resilient to the presence of interferers in spectrally noisy environments. The highly efficient transmitter has programmable output power up to 13.5 dBm and automatic power amplifier (PA) ramping to meet transient spurious specifications. The RF synthesizer comprises a voltage controlled oscillator (VCO), a low noise fractional-N phase-locked loop (PLL) and a loop filter, all of which are fully integrated and automatically calibrated. This agile frequency synthesizer facilitates the implementation of frequency-hopping spread spectrum (FHSS) systems.The smart wake mode (SWM) allows the ADF7024 to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption.The ADF7024 eases the processing burden of the host processor by integrating the lower layers of a typical communication protocol stack. The host processor can configure the ADF7024 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller).For more information, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package.APPLICATIONS Wireless sensor networks (WSNs) Home and building automation Asset tracking Process and building control Industrial control Internet of Things (IoT)

The ADG2188 is an analog cross point switch with an array size of 8 ? 8. The switch array is arranged so that there are eight columns by eight rows, for a total of 64 switch channels. The array is bidirectional, and the rows and columns can be configured as either inputs or outputs. Each of the 64 switches can be addressed and configured through the I2C-compatible interface. Standard, full speed, and high speed (3.4 MHz) I2C interfaces are supported. Any simultaneous switch combination is allowed. An additional feature of the ADG2188 is that switches can be updated simultaneously, using the LDSW command. In addition, a RESET option allows all of the switch channels to be reset/off. At power on, all switches are in the off condition. The device is packaged in a 32-lead, 5 mm ? 5 mm LFCSP_WQ.Applications AV switching in TV Automotive infotainment AV receivers CCTV Ultrasound applications KVM switching Telecom applications Test equipment/instrumentation PBX systems