Demonstration circuit 2047A-A is an IEEE802.3at compliant Power over Ethernet (PoE) Powered Device (PD) with support for 9-57VDC and 24VAC auxiliary supply input. It features the LT4276 PD interface and switching regulator controller, the LT4321 PoE ideal diode bridge controller, and the LT4320 ideal diode bridge controller.

DC204A-B: Demo Board for the LT1776 Wide Input Range, High Efficiency, Step-Down Switching Regulator.

The LT3753 is a current mode PWM controller optimized for an active clamp forward converter topology, allowing up to 100V input operation.A programmable volt-second clamp allows primary switch duty cycles above 50% for high switch, transformer and rectifier utilization. Active clamp control reduces switch voltage stress and increases efficiency. A synchronous output is available for controlling secondary side synchronous rectification.The LT3753 is available in a 38-lead plastic TSSOP package with missing pins for high voltage spacings.Applications Industrial, Automotive and Military Systems 48V Telecommunication Isolated Power Supplies

DC2062A-A: Demo Board for LT4363 High Voltage Surge Stopper with Current Limit.

The LTM4677 is a dual 18A or single 36A step-down ?Module? (power module) DC/DC regulator with 40ms turn0on time. It features remote configurability and telemetry-monitoring of power management parameters over PMBus?an open standard I2C-based digital interface protocol. The LTM4677 is comprised of fast analog control loops, precision mixedsignal circuitry, EEPROM, power MOSFETs, inductors and supporting components.The LTM4677?s 2-wire serial interface allows outputs to be margined, tuned and ramped up and down at programmable slew rates with sequencing delay times. Input and output currents and voltages, output power, temperatures, uptime and peak values are readable. Custom configuration of the EEPROM contents is not required. At start-up, output voltages, switching frequency, and channel phase angle assignments can be set by pin-strapping resistors. The LTpowerPlay? GUI and DC1613 USB-to-PMBus converter and demo kits are available.The LTM4677 is pin compatible with the LTM4676A (dual 13A) and is offered in a 16mm ? 16mm ? 5.01mm BGA package available with SnPb or RoHS compliant terminal finish.APPLICATIONS System Optimization, Characterization and Data Mining?in Prototype, Production and Field Environments Telecom, Datacom, and Storage Systems

The LTC2372-18 is a low noise, high speed, 8-channel 18-bit successive approximation register (SAR) ADC. Operating from a single 5V supply, the LTC2372-18 has a highly configurable, low crosstalk 8-channel input multiplexer, supporting fully differential, pseudo-differential unipolar and pseudo-differential bipolar analog input ranges. The LTC2372-18 achieves ?2.75LSB INL (maximum) in all input ranges, no missing codes at 18-bits and 100dB (fully differential)/ 95dB (pseudo-differential) SNR (typical).The LTC2372-18 has an onboard low drift (20ppm/?C max) 2.048V temperature-compensated reference and a single-shot capable reference buffer. The LTC2372-18 also has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic through which a sequencer with a depth of 16 may be programmed. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2372-18 dissipates only 27mW and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. A sleep mode is also provided to reduce the power consumption of the LTC2372-18 to 300?W for further power savings during inactive periods.Applications Programmable Logic Controllers Industrial Process Control High Speed Data Acquisition Portable or Compact Instrumentation ATE

The AD9162 is a high performance, 16-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2? interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.In baseband mode, wide bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of two carriers to full maximum spectrum of 1.794 GHz. A 2? interpolator filter (FIR85) enables the AD9161/AD9162 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode? operation, the AD9161/AD9162 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9161/AD9162 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.A serial peripheral interface (SPI) can configure the AD9161/AD9162 and monitor the status of all registers. The AD9161/AD9162 are offered in an 165-ball, 8.0 mm ? 8.0 mm, 0.5 mm pitch, CSP_BGA package and in an 169-ball, 11 mm ? 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option for the AD9162.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance with margin.Applications Broadband communications systems DOCSIS 3.1 cable modem termination system (CMTS)/video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure W-CDMA, LTE, LTE-A, point to point Instrumentation, automatic test equipment (ATE) Radars and jammers

The AD9171 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 6.2 GSPS. The device features an 8-lane, 15.4 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band direct to radio frequency (RF) wireless applications.The AD9171 features one complex data input channels per RF DAC. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, frequency planning. The device supports up to a 516 MSPS complex data rate per input channel.The AD9171 is available in a 144-ball BGA_ED package.PRODUCT HIGHLIGHTS Supports one complex data input channel per RF DAC at a maximum complex input data rate of 513 MSPS with 12-bitresolution and 516 MSPS with 16-bit resolution options. There is one independent NCO per input channel. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.?APPLICATIONS Wireless communications infrastructure Single-band base station radios Instrumentation, automatic test equipment (ATE)

The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The ?3 dB bandwidth of the ADC input is 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage referenceeases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signalprocessing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimationfilters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9208 has several functions that simplify the automatic gain control (AGC) function in acommunications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoidan overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9208 has flexible power-down options that allow significant power savings when desired. All of these features canbe programmed using a 3-wire serial port interface (SPI).The AD9208 is available in a Pb-free, 196-ball BGA, specified over the ?40?C to +85?C ambient temperature range. Thisproduct is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input ?3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers. Fast NCO switching enabled through GPIO pins. A SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature dioide for system thermal management. 12mm ? 12mm 196-Lead BGAApplications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9212 is an octal, 10-bit, 40 MSPS/65 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power,small size, and ease of use. Operating at a conversion rate of up to 65 MSPS, it is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock forthe appropriate LVDS serial data rate. A data clock (DCO)for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channelpower-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximizeflexibility and minimize system cost, such as programmableclock and data alignment and programmable digital test patterngeneration. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9212 is available in a RoHS-compliant, 64-lead LFCSP. It isspecified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS Small Footprint. Eight ADCs are contained in a small package. Low Power of 100 mW per Channel at 65 MSPS. Ease of Use. A data clock output (DCO) operates up to 300 MHz and supports double data rate (DDR) operation. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9222 (12-bit) and AD9252 (14-bit).APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment