The ADL5504 is a TruPwr? mean-responding (true rms) power detector for use in high frequency receiver and transmitter signal chains from 450 MHz to 6000 MHz. Requiring only a single supply between 2.5 V and 3.3 V, the detector draws less than 1.8 mA. The input is internally ac-coupled and has a nominal input impedance of 500 ?. The rms output is a linear-responding dc voltage with a conversion gain of 1.87 V/V rms at 900 MHz.The ADL5504 is a highly accurate, easy to use means of determining the rms of complex waveforms. It can be used for power measurements of both simple and complex waveforms but is particularly useful for measuring high crest factor (high peak-to-rms ratio) signals, such as W-CDMA, CDMA2000, WiMAX, WLAN, and LTE waveforms.The on-chip modulation filter provides adequate averaging for most waveforms. For more complex waveforms, an external capacitor at the FLTR pin can be used for supplementary signal demodulation. An on-chip, 100 ? series resistance at the output, combined with an external shunt capacitor, creates a low-pass filter response that reduces the residual ripple in the dc output voltage.The ADL5504 offers excellent temperature stability across a 30 dB range and near 0 dB measurement error across temperature over the top portion of the dynamic range. In addition to its temperature stability, the ADL5504 offers low process variations that further reduce calibration complexity.The power detector operates from ?40?C to +85?C and is available in a 6-ball, 0.8 mm ? 1.2 mm, wafer level chip scale package. It is fabricated on a high fT silicon BiCMOS process.Applications Power measurement of W-CDMA, CDMA2000, QPSK-/QAM-based OFDM (LTE and WiMAX), and other complex modulation waveforms RF transmitter or receiver power measurement

The ADL5724 is a narrow-band, high performance, low noise amplifier (LNA) targeting microwave radio link receiver designs. The monolithic silicon germanium (SiGe) design is optimized for microwave radio link bands ranging from 12.7 GHz to 15.4 GHz. The unique design offers a single-ended 50 ? input impedance and provides a 100 ? balanced differential output that is ideal for driving Analog Devices, Inc., differential downconverters and radio frequency (RF) sampling analog-to-digital converters (ADCs). This LNA provides noise figure performance that, in the past, required more expensive three-five (III-V) compounds process technology to achieve.The ADL5721 and ADL5723 to ADL5726 family of narrow-band LNAs are each packaged in a tiny, thermally enhanced, 2.00 mm ? 2.00 mm LFCSP package. The ADL5721 and ADL5723 to ADL5726 family operates over the temperature range of ?40?C to +85?C.Applications Point to point microwave radios Instrumentation Satellite communications (SATCOM) Phased arrays

The ADP1046A is a flexible, digital secondary side controller designed for ac-to-dc and isolated dc-to-dc secondary sideapplications. The ADP1046A is pin-compatible with theADP1043A and offers several enhancements and new features,including voltage feedforward and improved loop response to maximize efficiency.The ADP1046A is optimized for minimal component count,maximum flexibility, and minimum design time. Featuresinclude local and remote voltage sense, primary and secondary side current sense, digital pulse-width modulation (PWM)generation, current sharing, and redundant OrFET control. The control loop digital filter and compensation terms are integrated and can be programmed over the I2C interface. Programmableprotection features include overcurrent protection (OCP), over-voltage protection (OVP), undervoltage lockout (UVLO), and overtemperature protection (OTP).The built-in EEPROM provides extensive programming of theintegrated loop filter, PWM signal timing, inrush current, andsoft start timing and sequencing. Reliability is improved through a built-in checksum and programmable protection circuits.A comprehensive GUI is provided for easy design of loop filter characteristics and programming of the safety features.The industry-standard I2C bus provides access to the many monitoring and system test functions.The ADP1046A is available in a 32-lead LFCSP and operatesfrom a single 3.3 V supply.APPLICATIONS AC-to-DC power supplies Isolated dc-to-dc power supplies Redundant power supply systems Server, storage, network, and communications infrastructure

The ADP195 is a high-side load switch designed for operation between 1.1 V to 3.6 V and protected against reverse current flow from output to input. This load switch provides power domain isolation helping extended power domain isolation. The device contains a low on-resistance, P-channel MOSFET that supports over 500 mA of continuous current and minimizes power loss. The low 1 ?A of quiescent current and ultralow shutdown current make the ADP195 ideal for battery-operated portable equipment. The built-in level shifter for enable logic makes the ADP195 compatible with many processors and GPIO controllers.In addition to operating performance, the ADP195 occupies minimal printed circuit board (PCB) space with an area of less than 1.0 mm2 and a height of 0.60 mm.It is available in an ultrasmall 1 mm ? 1 mm, 4-ball, 0.5 mm pitch WLCSP. A 6-lead 2 mm ? 2 mm ? 0.55 mm, 0.65 mm pitch LFCSP is also available.APPLICATIONS Mobile phones Digital cameras and audio devices GPS devices Personal media players Portable and battery-powered equipment

The 300 mA, adjustable dual output ADP223 / ADP225 and fixed dual output ADP222 / ADP224 combine high PSRR, low noise, low quiescent current, and low dropout voltage in a voltage regulator that is ideally suited for wireless applications with demanding performance and board space requirements.The low quiescent current, low dropout voltage, and wide input voltage range of the ADP222 / ADP223 / ADP224 / ADP225 extend the battery life of portable devices.The ADP222 / ADP223 / ADP224 / ADP225 maintain power supply rejection greater than 60 dB for frequencies as high as 100 kHz while operating with a low headroom voltage. The ADP222 / ADP223 / ADP224 / ADP225 offer much lower noise performance than competing LDOs without the need for a noise bypass capacitor. Overcurrent and thermal protection circuitry prevent damage in adverse conditions.The ADP224 and ADP225 are identical to the ADP222 and ADP223, respectively, but with the addition of a quick output discharge (QOD) feature.The ADP222 / ADP223 / ADP224 / ADP225 are available in a small 8-lead, 2 mm?? 2 mm LFCSP package and are stable with tiny 1 ?F, ?30% ceramic output capacitors, resulting in the smallest possible board area for a wide variety of portable power needs.APPLICATIONS Portable and battery-powered equipment Portable medical devices Post dc-to-dc regulation Point of sale terminals Credit card readers Automatic meter readers Wireless network equipment

The ADP5065 charger is fully compliant with the USB 2.0, USB 3.0, and USB Battery Charging Specification 1.1 and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port.The ADP5065 operates from a 4 V to 5.5 V input voltage range but is tolerant of voltages of up to 20 V. This alleviates the concerns about the USB bus spiking during disconnect or connect scenarios.The ADP5065 also features an internal FET between the dc-to-dc charger output and the battery. This permits battery isolation and, hence, system powering under a dead battery or no battery scenario, which allows for immediate system function on connection to a USB power supply.Based on the type of USB source, which is detected by an external USB detection chip, the ADP5065 can be set to apply the correct current limit for optimal charging and USB compliance.The ADP5065 comes in a very small and low profile 20-lead WLCSP (0.5 mm pitch spacing) package.The overall solution requires only five small, low profile external components consisting of four ceramic capacitors (one of which is the battery filter capacitor), one multilayer inductor. In addition to these components, there is one optional dead battery situation default setting resistor. This configuration enables a very small PCB area to provide an integrated and performance enhancing solution to USB battery charging and power rail provision. APPLICATIONS Digital still cameras Digital video cameras Single cell Li-Ion portable equipment PDA, audio, GPS devices Mobile phones?

The ADP5076 is a dual, high performance, dc-to-dc regulator that generates independently regulated positive and negative rails. The input voltage range of 2.85 V to 5.5 V supports a wide variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to +35 V and a negative output voltage down to ?30 V.?The ADP5076 operates at a pin selected 1.2 MHz or 2.4 MHz switching frequency. The ADP5076 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement programmable slew rate control circuitry for the metal-oxide semiconductor field effect transistor (MOSFET) driver stage to reduce electromagnetic interference (EMI). Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and negative supply first.?The ADP5076 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. Other key safety features in the ADP5076 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5076 is available in a 20-ball wafer level chip scale package (WLCSP) and is rated for a ?40?C to +125?C junction temperature range.?Applications Bipolar amplifiers, ADCs, DACs, and multiplexers Charge coupled device (CCD) bias supply Optical module supply RF power amplifier bias Time of flight module supply

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The AD9375 is a highly integrated, wideband radio frequency (RF) transceiver offering dual-channel transmitters (Tx) and receivers (Rx), integrated synthesizers, a fully integrated digital predistortion (DPD) actuator and adaptation engine, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G small cell and massive multiple input, multiple output (MIMO) equipment in both frequency division duplex (FDD) and time division duplex (TDD) applications. The AD9375 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The DPD algorithm supports linearization on signal bandwidths up to 40 MHz depending on the power amplifier (PA) characteristics (for example, two adjacent 20 MHz carriers). The IC supports Rx bandwidths up to 100 MHz. It also supports observation receiver (ORx) and Tx synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete Rx and Tx subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.An ORx channel with two inputs is included to monitor each Tx output and implement calibration applications. This channel also connects to three sniffer receiver (SnRx) inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the Tx, the Rx, the ORx, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.The device contains a fully integrated, low power DPD actuator and adaptation engine for use in PA linearization. The DPD feature enables use of high efficiency PAs, significantly reducing the power consumption of small cell base station radios while also reducing the number of JESD204B lanes necessary to interface with baseband processors.A 1.3 V supply is required to power the AD9375 core, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9375 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G small cell base stations (BTS) 3G/4G massive MIMO/active antenna systems