The HMC504LC4B is a GaAs MMIC Low NoiseWideband Amplifier housed in a leadless 4?4 mm ceramicsurface mount package. The amplifier operatesbetween 14 and 27 GHz, providing up to 19 dB ofsmall signal gain, 2.2 dB noise figure, and output IP3of +26 dBm, while requiring only 90 mA from a +4Vsupply. The P1dB output power of up to +17 dBmenables the LNA to function as a LO driver for balanced,I/Q or image reject mixers. The HMC504LC4Balso features I/Os that are DC blocked and internallymatched to 50 ?, making it ideal for high capacitymicrowave radios or VSAT applications. This versatileLNA is also available in die form as the HMC-ALH476.APPLICATIONSThis HMC504LC4B is ideal for: Point-to-Point Radios Point-to-Multi-Point Radios Military & Space Test Instrumentation

The HMC753 is a GaAs MMIC Low Noise Wideband Amplifier housed in a leadless 4x4 mm plastic surface mount package. The amplifier operates between 1 and 11 GHz, providing up to 16.5 dB of small signal gain, 1.5 dB noise figure, and output IP3 of +30 dBm, while requiring only 55 mA from a +5V supply. The P1dB output power of up to +18 dBm enables the LNA to function as a LO driver for balanced, I/Q or image reject mixers. The HMC753 also features I/Os that are DC blocked and internally matched to 50 Ohms, making it ideal for high capacity microwave radios or VSAT applications. This versatile LNA is also available in die form as the?HMC-ALH444.Applications Point-to-Point Radios Point-to-Multi-Point Radios Military & Space Test Instrumentation.

The HMC859LC3 is a Divide-by-8 with Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications. The HMC859LC3 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All input signals to the HMC859LC3 are terminated with 50 ? to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50 ? terminated system, while DC blocking capacitors may be used if the terminating system is 50 ? to a non-ground DC voltage. The HMC859LC3 operates from a single -3.3 V DC supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS High Speed Frequency Divider?(up to 26 GHz) Clock Synthesis Phase Locked Loops Broadband Test & Measurement

The HMC741 is an InGaP Heterojunction Bipolar Transistor (HBT) Gain Block MMIC SMT amplifier covering 0.05 to 3 GHz. Packaged in an industry standard SOT89, the amplifier can be used as a cascadable 50 Ohm RF or IF gain stage as well as a PA or LO driver with up to +18.5 dBm output power. The HMC741 offers 20 dB of gain with a +42 dBm output IP3 at 200 MHz, and can operate directly from a +5V supply. The HMC741 exhibits excellent gain and output power stability over temperature, while requiring a minimal number of external bias components.Applications Cellular/3G & WiMAX/4G Fixed Wireless & WLAN CATV, Cable Modem & DBS Microwave Radio & Test Equipment IF & RF Applications

The AD9554-1 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems,including synchronous optical networks (SONET/SDH). The AD9554-1 generates an output clock synchronized to up to four external input references. The digital PLLs (DPLLs) allowreduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdovercircuitry of the AD9554-1 continuously generates a low jitteroutput clock even when all reference inputs have failed.The AD9554-1 operates over an industrial temperature range of ?40?C to +85?C. The AD9554 is a version of this device with two outputs per PLL. If a single or dual DPLL version of thisdevice is needed, refer to the AD9557 or AD9559, respectively.Applications Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Cable infrastructure? Data communications? Professional video

The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9557 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9557 continuously generates a low jitter output clock even when all reference inputs have failed.The AD9557 operates over an industrial temperature range of ?40?C to +85?C. If more inputs/outputs are needed, refer to the AD9558 for the four-input/six-output version of the samedevice.Applications Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping Cleanup of reference clock jitter SONET/SDH/OTN clocks up to 100 Gbps, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Wireless base station controllers Cable infrastructure Data communications

The AD9609 is a monolithic, single channel 1.8 V supply, 10-bit,20/40/65/80 MSPS analog-to-digital converter (ADC). It featuresa high performance sample-and-hold circuit and on-chip voltagereference.The product uses multistage differential pipeline architecturewith output error correction logic to provide 10-bit accuracy at80 MSPS data rates and to guarantee no missing codes over thefull operating temperature range.The ADC contains several features designed to maximize flexibilityand minimize system cost, such as programmable clock and dataalignment and programmable digital test pattern generation. Theavailable digital test patterns include built-in deterministic andpseudorandom patterns, along with custom user-defined testpatterns entered via the serial port interface (SPI).A differential clock input with selectable internal 1 to 8 divide ratiocontrols all internal conversion cycles. An optional duty cyclestabilizer (DCS) compensates for wide variations in the clock dutycycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, ortwos complement format. A data output clock (DCO) is providedto ensure proper latch timing with receiving logic. Both 1.8 V and3.3 V CMOS levels are supported.The AD9609 is available in a 32-lead RoHS-compliant LFCSPand is specified over the industrial temperature range (?40?Cto +85?C).APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imagingPRODUCT HIGHLIGHTS1. The AD9609 operates from a single 1.8 V analog powersupply and features a separate digital output driver supplyto accommodate 1.8 V to 3.3 V logic families.2. The sample-and-hold circuit maintains excellent performancefor input frequencies up to 200 MHz and is designed for lowcost, low power, and ease of use.3. A standard serial port interface supports various productfeatures and functions, such as data output formatting,internal clock divider, power-down, DCO and data output(D9 to D0) timing and offset adjustments, and voltagereference modes.4. The AD9609 is packaged in a 32-lead RoHS compliantLFCSP that is pin compatible with the AD9629 12-bit ADCand the AD9649 14-bit ADC, enabling a simple migrationpath between 10-bit and 14-bit converters sampling from20 MSPS to 80 MSPS.

The AD9634 is a 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9634 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data are routed directly to the external 12-bit LVDS output port.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire, SPI-compatible serial interface.The AD9634 is available in a 32-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 350 MHz. 3-pin, 1.8V SPI port for register programming and readback. Pin compatibility with the?AD9642, allowing a simple migration up to 14 bits, and with the?AD6672. APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications

The AD9642 is a 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9642 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data is routed directly to the external 14-bit LVDS output port.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9642 is available in a 32-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent. APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applicationsPRODUCT HIGHLIGHTS Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 350 MHz. 3-pin, 1.8 V SPI port for register programming and readback. Pin compatibility with the AD9634, allowing a simple migration from 14 bits to 12 bits, and with the AD6672.

The AD9643 is a dual, 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9643 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC output data is routed directly to the external, 14-bit, LVDS output port and formatted as either interleaved or channel multiplexed.Flexible power-down options allow significant power savings, when desired.Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9643 is available in a 64-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C. Thisproduct is protected by a U.S. patent.Product Highlights Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. SYNC input allows synchronization of multiple devices. 3-pin, 1.8 V SPI port for register programming and register readback. Pin compatibility with the AD9613, allowing a simple migration down from 14 bits to 12 bits. This part is also pin compatible with the AD6649 and the AD6643.Applications Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications