The AD9531 provides a multioutput clock generator function and three on-chip phase-locked loop (PLL) cores with SPI programmable output frequencies and formats.PLL1 provides two reference inputs and 10 outputs and includes four user selectable loop configurations. The PLL has a fully integrated loop filter requiring only a single external capacitor (or a series RC network). PLL1 provides a wide range of output frequencies up to 400 MHz and is capable of operating with an external voltage controlled crystal oscillator (VCXO) and loop filter, instead of the integrated voltage controlled oscillator (VCO) and loop filter.PLL2 is an integer-N PLL providing a single reference input and 12 outputs. PLL2 synthesizes output frequencies up to 400 MHz from the REF2_x source and synchronizes the output clocks to the input reference.PLL3 provides a single reference input and two outputs. PLL3 synthesizes output frequencies up to 400 MHz from the REF3_x source and synchronizes the output clocks to input reference.The AD9531 is available in an 88-lead LFCSP and is specified over the ?40?C to +85?C operating temperature range.Throughout this data sheet, multifunction pins, such as LOR/M4, are referred to either by the entire pin name or by a single function of the pin (for example, LOR, when only that function is relevant). In other cases, the text and figures of this data sheet contain references to a channel rather than a pin. For example, REF_A refers to the REF_A channel rather than the REF_AP and REF_AN pins. Likewise, OUT3_1 refers to Channel 1 of PLL3 rather than the OUT3_1P and OUT3_1N pins. Additionally, an abbreviated notation for a pin pair replaces an explicit reference to a each pin (for example, REF_Ax signifies the REF_AN and REF_AP pins.).Applications Radio equipment controller clocking Low jitter/phase noise clock generation and distribution Clock generation and translation for SONET, 10GE, 10G FC, and other 10 Gbps protocols 40 Gbps/100 Gbps networking line cards, including SONET, synchronous ethernet, OTU2/3/4 Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures Ethernet line cards, switches, and routers SATA and PCI-express

The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clockeven when all references have failed by means of a digitallycontrolled loop and holdover circuitry.The AD9548 operates over an industrial temperature range of?40?C to +85?C.ApplicationsNetwork synchronizationCleanup of reference clock jitterGPS 1 pulse per second synchronizationSONET/SDH clocks up to OC-192, including FECStratum 2 holdover, jitter cleanup, and phase transient controlStratum 3E and Stratum 3 reference clocksWireless base stations, controllersCable infrastructureData communications

DC906A: Demo Board for the LTC4306 4-Channel, 2-Wire Bus Multiplexer with Capacitance Buffering.

The LTC3204-3.3/LTC3204-5/LTC3204B-3.3/LTC3204B-5 are low noise, constant frequency (1.2MHz) switched capacitor voltage doublers. The LTC3204-3.3/ LTC3204B-3.3 can produce a regulated output voltage of 3.3V from a minimum input voltage of 1.8V (2 alkaline cells) whereas the LTC3204-5/LTC3204B-5 can produce 5V from a minimum of 2.7V (Li-Ion battery) input.LTC3204-3.3/LTC3204-5 feature automatic Burst Mode? operation at light loads to maintain low supply current whereas LTC3204B-3.3/LTC3204B-5 feature constant frequency operation at any load. Built-in soft-start circuitry prevents excessive inrush current during start-up. Thermal shutdown and current-limit circuitry allow the parts to survive a continuous short-circuit from VOUT to GND.High switching frequency minimizes overall solution footprint by allowing the use of tiny ceramic capacitors. In shutdown, the load is disconnected from the input and the quiescent current is reduced to <1?A.The LTC3204-3.3/LTC3204-5/LTC3204B-3.3/LTC3204B-5 are available in a low pro?le (0.75mm) 6-lead 2mm ? 2mm DFN package.*Protected by U.S. Patents including 6411531.Applications 2 AA Cell to 3.3V Li-Ion to 5V USB On-The-Go Devices White LED Drivers Handheld Devices

Demonstration circuit 916 is a low noise regulated charge pump featuring the LTC3204B (constant frequency switching) in the 2X2 DFN package. There are two assembly versions, DC916A-A and DC916A-B for the LTC3204B-5 (5V output) and LTC3204B-3.3 (3.3V output) respectively. The DC916A-B produces a regulated 3.3V output from a 1.8V to 4.5V input. The guaranteed output current is 50mA from VIN between 1.9V and 4.5V, and 40mA for VIN less than 1.9V. The circuit requires only three tiny 0603 surface mount capacitors and uses minimal board space. No inductor or diodes are needed. The circuit features automatic Burst Mode® operation at light loads to maintain low supply current.

DC918C-H: Demo Board for the LTC2207-14 14-Bit, 105Msps ADC.

Demonstration circuit 925 features the LT3489EMS8E in a circuit specifically designed to drive large TFT/LCD displays. The demo circuit demonstrates small size and low component count in a Boost Circuit. It converts a 3.3V-6V input to 8V at 600mA, 23V at 10mA and -8V at 20mA. Since the maximum Vin of the LT3489 is 16V, this Demo circuit will work well at higher inputs. The only limitation is that the input has to be lower than the Boost converter output (8V) in order to stay in regulation. This circuit is designed to demonstrate the capacitor programmable Soft-Start feature, advantages of the 2MHz constant switching frequency and the internal 2.5A, 40V switch.

Demonstration circuit 932A is an adjustable 1A linear regulator featuring LT3022. The LT3022 is a very low dropout voltage (VLDO™) linear regulator that operates from input supplies down to 0.9V. The device supplies 1A of output current with 145mV typical dropout voltage. The LT3022 is ideal for low input voltage to low output voltage applications, providing comparable electrical efficiency to a switching regulator. The demo board has an input voltage range from 1V to 10V and provides a jumper-selectable output voltage of 0.9V, 1V, 1.2V, 1.5V, 1.8V or a user-defined value down to 200mV. The regulator optimizes stability and transient response with low ESR ceramic output capacitors as small as 10µF. Other LT3022 features include 0.05% typical line regulation and 0.05% typical load regulation. In shutdown, the quiescent current typically drops to 7.5µA. Internal protection circuitry includes reverse-battery protection, current limiting, thermal limiting with hysteresis and reverse-current protection.

DC935A: Demo Board for the LTC2605 Octal I2C 16-Bit Rail-to-Rail DACs in 16-Lead SSOP.

The LTC2609/LTC2619/LTC2629 are quad 16-, 14- and 12- bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a 16?lead SSOP package. They have built-in high performance output buffers and are guaranteed monotonic.These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive and load regulation in single-supply, voltage- output DACs.The parts use a 2-wire, I2C compatible serial interface. The LTC2609/LTC2619/LTC2629 operate in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz).The LTC2609/LTC2619/LTC2629 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero-scale; after power-up, they stay at zero-scale until a valid write and update take place. The power-on reset circuit resets the LTC2609-1/LTC2619?1/ LTC2629-1 to mid-scale. The voltage outputs stay at midscale until a valid write and update take place.Applications Mobile Communications Process Control and Industrial Automation Automatic Test Equipment and Instrumentation