The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The AD9375 is a highly integrated, wideband radio frequency (RF) transceiver offering dual-channel transmitters (Tx) and receivers (Rx), integrated synthesizers, a fully integrated digital predistortion (DPD) actuator and adaptation engine, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G small cell and massive multiple input, multiple output (MIMO) equipment in both frequency division duplex (FDD) and time division duplex (TDD) applications. The AD9375 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The DPD algorithm supports linearization on signal bandwidths up to 40 MHz depending on the power amplifier (PA) characteristics (for example, two adjacent 20 MHz carriers). The IC supports Rx bandwidths up to 100 MHz. It also supports observation receiver (ORx) and Tx synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete Rx and Tx subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.An ORx channel with two inputs is included to monitor each Tx output and implement calibration applications. This channel also connects to three sniffer receiver (SnRx) inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the Tx, the Rx, the ORx, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.The device contains a fully integrated, low power DPD actuator and adaptation engine for use in PA linearization. The DPD feature enables use of high efficiency PAs, significantly reducing the power consumption of small cell base station radios while also reducing the number of JESD204B lanes necessary to interface with baseband processors.A 1.3 V supply is required to power the AD9375 core, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9375 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G small cell base stations (BTS) 3G/4G massive MIMO/active antenna systems

The ADV3202/ADV3203 are 32 ? 16 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input forac-coupled applications and a 2:1 on-screen display (OSD) insertion mux. With ?48 dB of crosstalk and ?80 dB isolationat 5 MHz, the ADV3202/ADV3203 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3202/ADV3203 ideal for both composite and component video switching.The 16 independent output buffers of the ADV3202/ADV3203 can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus if building a larger array. The ADV3202 has a gain of +1 while the ADV3203 has a gain of +2 for ease of use in back-terminated load applications. A single +5 V supply, dual ?2.5 V supplies, or dual ?3.3 V supplies can be used while consuming only 195 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, that can accommodate daisy chaining of several devices.The ADV3202/ADV3203 are packaged in a 176-lead exposed pad LQFP package (24 mm ? 24 mm) and are available over the extended industrial temperature range of ?40?C to +85?C.Applications CCTV surveillance Routing of high speed signals ? ? ? Composite video (NTSC, PAL, S, SECAM) ? ? ? RGB and component video routing ? ? ? Compressed video (MPEG, wavelet) Video conferencingData Sheet, Rev 0, 11/2008

DC1086A: Demo Board for LTC3546 Dual Synchronous, 3A/1A or 2A/2A Configurable Step-Down DC/DC Regulator.

The LTC3822-1 is a synchronous step-down switching regulator controller that drives external N-channel power MOSFETs using few external components. The constant frequency current mode architecture with MOSFET VDS sensing eliminates the need for sense resistors and improves efficiency.Burst Mode operation provides high efficiency at light loads. The 99% maximum duty cycle provides low dropout operation, extending operating time in battery-powered systems.The operating frequency can be programmed up to 750kHz, allowing the use of small surface mount inductors and capacitors. For noise sensitive applications, the LTC3822-1 can be synchronized to an external clock from 250kHz to 750kHz.The LTC3822-1 is available in the tiny footprint thermally enhanced 12-pin DFN package or 16-pin narrow SSOP package. Features LTC3822 Internal soft-start, 34?A in sleep mode LTC3822-1 External soft start, selectable pulse skip/Burst Mode operation, power good (SSOP-16 package only), 105?A in sleep mode Applications Single Cell Li-Ion Powered Systems 3.3VIN Systems

The LTC6101/LTC6101HV are versatile, high voltage, high side current sense amplifiers. Design flexibility is provided by the excellent device characteristics; 300?V Max offset and only 375?A (typical at 60V) of current consumption. The LTC6101 operates on supplies from 4V to 60V and LTC6101HV operates on supplies from 5V to 100V.The LTC6101 monitors current via the voltage across an external sense resistor (shunt resistor). Internal circuitry converts input voltage to output current, allowing for a small sense signal on a high common mode voltage to be translated into a ground referenced signal. Low DC offset allows the use of a small shunt resistor and large gain-setting resistors. As a result, power loss in the shunt is reduced.The wide operating supply range and high accuracy make the LTC6101 ideal for a large array of applications from automotive to industrial and power management. A maximum input sense voltage of 500mV allows a wide range of currents to be monitored. The fast response makes the LTC6101 the perfect choice for load current warnings and shutoff protection control. With very low supply current, the LTC6101 is suitable for power sensitive applications.The LTC6101 is available in 5-lead SOT-23 and 8-lead MSOP packages.Applications Current Shunt Measurement Battery Monitoring Remote Sensing Power Management

The LT1328 is a photodiode receiver that supports IrDA? data rates up to 4Mbps as well as other modulation methods such as Sharp ASK and TV remote control. The LT1328 MSOP contains all the necessary circuitry to convert current pulses from an external photodiode to a digital TTL output while rejecting unwanted lower frequency interference. The LT1328 plus five external components is all that is required to make an IrDA compatible receiver.Power requirements for the LT1328 are minimal?a single 5V supply and 2mA of quiescent current. Internal high-pass filtering attenuates interfering signals such as sunlight, incandescent and fluorescent lamps and is selectable at Pin 7 for low or high data rates. The LT1328?s ease of use and flexibility make it an ideal solution for numerous other photodiode receiver applications. The LT1328 is available in the SO-8 as well as the tiny MSOP for size-critical applications.Applications IrDA Applications Sharp/Newton TV Remote Noncontact Telemetry Wireless Slave for Photographic Flash Keyless Entry Optical Data Transfer Infrared Home Control Systems

The LTC3230 is a low noise charge pump DC/DC converter designed to drive 4 Main LEDs and 1 Sub LED, plus two 200mA linear regulators to provide additional system power. The LTC3230 charge pump requires only four small ceramic capacitors and one current set resistor to form a complete LED power supply and current controller.Built-in soft-start circuitry prevents excessive inrush cur- rent during start-up and mode changes. High switching frequency enables the use of small external capacitors. Main and Sub full-scale current settings are programmed by a single external resistor. Charge pump efficiency is optimized based on the voltage across the LED current sources. The part powers up in 1x mode and automatically switches to the next higher mode, 1.5x and subsequently 2x, whenever any LED current source approaches dropout.Two 200mA linear regulators have independent enable and output voltage select pins. Each regulator can be set to one of three pre-selected output voltages with tri-level input pins. The regulators may be enabled independently of the charge pump.The LTC3230 is available in a low profile (0.75mm) 3mm x 3mm 20-lead QFN package.Applications Multi-LED Driver and Dual LDO Supplies for Cell Phone, PDA, Digital Camera and PND Applications?

Demonstration circuit 1244 is a Low Quiescent Current, Dual Output Synchronous Buck Converter featuring the LTC3890EGN-1. DC1244 converts a 4.5V to 60V voltage source to 3.3V at 5.0A and 8.5V at 3.0A. When the input voltage is close to or below 9V, the 8.5V output enters dropout mode.The "-1" version has a fixed current limit and current foldback. See data sheet for other differences.

Demonstration circuit DC1256A is a single-battery standalone battery charger that can support any version ofthe LTC4012 family of parts. The LTC4012 family of charge controller IC’s do not support charge termination for any specific battery chemistry. Any charger termination, if necessary, is accomplished outside the LTC4012 with the most common method using a microcontroller. The DC1256A is shipped with the LTC4012-2 installed,which is optimized for Li-ion charge applications using a 4.2V/cell float voltage.The charger output voltage is programmed by jumpers to support 1, 2, 3 and 4 series stack Li-ion batteries. The input voltage is can be between 6V and 20V with the maximum voltage of the Demo Board design limited by the input capacitor voltage ratings. To reach full charge,the minimum input voltage must be greater than the float voltage setting.