LED Lighting Development Tools Inverse Buck 35W LED current controlled by HVLED002 Analog/PWM dimming

Plug-in Module for STM8S-DISCOVERY Interface for DALI Communication

The AD5316R, a member of the nanoDAC? family, is a low power,quad, 10-bit buffered voltage output DAC. The device includesa 2.5 V, 2 ppm/?C internal reference (enabled by default) and again select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V(gain = 2). The device operates from a single 2.7 V to 5.5 V supply,is guaranteed monotonic by design, and exhibits less than 0.1%FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm ? 3 mm lead lead frame chip scale package (LFCSP) and in a thin shrink small outline package (TSSOP).The AD5316R also incorporates a power-on reset circuit and aRSTSEL pin. The RSTSEL pin ensures that the DAC outputs powerup to zero scale or midscale and remain at that level until a validwrite takes place. The device contains a per channel power-down feature that reduces the current consumption of the device in power-down mode to 4 ?A at 3 V.The AD5316R uses a versatile 2-wire serial interface that operatesat clock rates up to 400 kHz and includes a VLOGIC pin intendedfor 1.8 V/3 V/5 V logic.Product Highlights Precision DC Performance. Total unadjusted error (TUE): ?0.1% of FSR maximum Offset error: ?1.5 mV maximum Gain error: ?0.1% of FSR maximum Low Drift 2.5 V On-Chip Reference. 2 ppm/?C typical temperature coefficient 5 ppm/?C maximum temperature coefficient Two Package Options. 3 mm ? 3 mm, 16-lead LFCSP 16-lead TSSOPApplications Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems

The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference.Each output divider and feedback divider ratio is preprogrammed for the required output rates. No external loop filter components are required, thus conserving valuable design time and board space.The AD9571 is available in a 40-lead 6 mm ? 6 mm lead frame chip scale package and can be operated from a single 3.3 V supply. The operating temperature range is ?40?C to +85?C.APPLICATIONS Ethernet line cards, switches, and routers SCSI, SATA, and PCI-express PCI support included Low jitter, low phase noise clock generation

DEM-VCA-SO-1B

DEVELOPMENT KIT DIGITAL POWER

Multiple Function Sensor Development Tools LSM6DSV16BX adapter board for a standard DIL24 socket

Position Sensor Development Tools LPS33W adapter board for a standard DIL24 socket

KSZ8852HLE EVAL BOARD