Demonstration circuit 561 is a high current stepdown PolyPhaseTM converter featuring the LTC3731 three-phase synchronous buck controller. The input voltage is from 10V to 14V and output is 1.5V. DC561A-A can provide up to 180A output current with a 12-phase buck circuit, while DC561A-B is a 6-phase buck converter with up to 90A output current. An optional VID controller circuit is available on both DC561A-A and DC561A-B demo circuits for output voltage programming.

DC699A-A: Demo Board for the LTC1749 12-Bit, 80Msps Wide Bandwidth ADC.

The LT6402-20 is a low distortion, low noise differential ampli?er/ADC driver for use in applications from DC to 300MHz. The LT6402-20 has been designed for ease of use, with minimal support circuitry required. Exceptionally low input-referred noise and low distortion (with either single-ended or differential inputs) make the LT6402-20 an excellent solution for driving high speed 12-bit and 14-bit ADCs. In addition to the normal unfiltered outputs (+OUT and ?OUT), the LT6402-20 has a built-in 75MHz differential low pass filter and an additional pair of filtered outputs (+OUTFILTERED, ?OUTFILTERED) to reduce external filtering components when driving high speed ADCs. The output common mode voltage is easily set via the VOCM pin, eliminating an output transformer or AC-coupling capacitors in many applications.The LT6402-20 is designed to meet the demanding requirements of communications transceiver applications. It can be used as a differential ADC driver, a general-purpose differential gain block, or in other applications requiring differential drive. The LT6402-20 can be used in data acquisition systems required to function at frequencies down to DC.The LT6402-20 operates on a 5V supply and consumes 30mA. It comes in a compact 16-lead 3mm ? 3mm QFN package and operates over a ?40?C to 85?C temperature range.Applications Differential ADC Driver for: Imaging Communications Differential Driver/Receiver Single Ended to Differential Conversion Differential to Single Ended Conversion Level Shifting IF Sampling Receivers SAW Filter Interfacing/Buffering

The HMC1034LP6GE is a low-noise, wide-band clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 125MHz and 3GHz range. The HMC1034LP6GE features low noise Phase Detector (PD) and Delta-Sigma modulator, capable of operating at up to 100MHz, permit wider loop-bandwidths with excellent spectral performance.The HMC1034LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (<-165dBc/Hz) makes the HMC1034LP6GE an ideal source for a variety of applications?such as clock references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SERDES) circuits, FPGAs and processors. The HMC1034LP6GE can also be used as an LO for 10G/40G/100G optical modules and transponders, as well as primary reference clock for 10G/40G/100G line cards, and for jitter attenuation and frequency translation.The differential output of the HMC1034LP6GE includes a 2-bit output amplitude control which may be set via the SPI serial programming interface, and an output Mute function. The Delta-Sigma Modulator of the HMC1034LP6GE features Hittite?s Exact Frequency Mode, which enables users to generate output frequencies with close to 0 Hz frequency error.APPLICATIONS 10G/40G/100G Optical Modules, Transponders,?Line Cards OTN and SONET/SDH Applications 1G/10G Ethernet Line Cards High Frequency Processor Clocks Low Jitter SAW Oscillator Replacement? Fiber Channel Interface Clocks Cellular/4G Infrastructure DDS Replacement 10G Optical Modules,?Transponders, Line Cards

The HMC1133LP5E is a 6-bit digital phase shifter which is rated from 4.0 to 7 GHz, providing 360 degrees of phase coverage, with a LSB of 5.625 degrees. The HMC1133LP5E features very low RMS phase error of 2.8 degrees and extremely low insertion loss variation of ?0.4 dB across all phase states. This high accuracy phase shifter is controlled with positive control logic of 0/+5V The HMC1133LP5E is housed in a compact 5x5 mm plastic leadless SMT package and is internally matched to 50 Ohms with no external components.Applications EW Receivers Weather & Military Radar Satellite Communications Beamforming Modules Phase Cancellation

The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).The ?-?-based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures.Applications GSM/EDGE base stations PHS base stations Instrumentation and test equipment

The ADN2817/ADN2818 provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ ADN2818 automatically lock to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted.This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver.The ADN2817/ADN2818 have many optional features available through an I2C interface. For example, the user can read back the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. A BERMON circuit provides an estimate of the received bit error rate (BER) without interruption of the data. Alternatively, the user can adjust the data sampling phase to optimize the received BER.The ADN2817/ADN2818 are available in a compact 5 mm ? 5 mm, 32-lead, lead frame chip scale package.ApplicationsSONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates Fibre Channel, 2? Fibre Channel, GbE, HDTV, and others WDM transponders Regenerators/repeaters Test equipment

SmartMesh IP wireless sensor networks are self managing, low power internet protocol (IP) networks built from wireless nodes called motes.The LTP5902-IPM is printed circuit board assembly (PCBA) product with on-board chip antenna in the Eterna? family of IEEE 802.15.4e solutions, featuring a highly integrated, low power radio design as well as an ARM Cortex-M3 32-bit microprocessor running SmartMesh IP embedded networking software. The LTP5902-IPM, at 37mm ? 24mm, is built for surface-mount assembly.With SmartMesh IP time-synchronized networks, all motes in the network may route, source or terminate data, while providing many years of battery powered operation. SmartMesh IP is a highly flexible network with proven reliability and low power performance in an easy-to-integrate platform.The LTP5902-IPM?s behavior in a SmartMesh IP network is determined by the choice of SmartMesh IP network software loaded: Wireless Mote, EManager, Access Point Mote in a SmartMesh IP network. The SmartMesh IP software provided with the LTP5902-IPM is fully tested and validated, and is readily configured via a software Application Programming Interface. Once you have purchased SmartMesh IP products, the SmartMesh IP stack binaries may be downloaded via your myAnalog account. The pin signaling behavior of the LTP5902IPC-IPMA hardware is determined by the software loaded and is described in detail in the following product datasheets: LTP5902-IPM = LTP5902IPC-IPMA hardware + SmartMesh IP ?Mote? Software ? LTP5902-IPM Datasheet LTP5902-IPR = LTP5902IPC-IPMA hardware + SmartMesh IP EManager Software ? LTP5902-IPR Datasheet LTP5902-IPA = LTP5902IPC-IPMA hardware + SmartMesh IP Access Point Software ? LTP5902-IPA Datasheet Network Features Feature Benefit >99.999% Network Reliability Avoids communications dropouts common with other wireless networks NIST-certified AES-128 bit Encryption Data protected by end-to-end encryption, message integrity checking and device authentication Scalable Uses time-slotted channel-hopping protocol to avoid in-network collisions to maximize scale while minimizing power and latency-hungry transmission retries due to congestion Bidirectional Communications Ideal for both monitoring and control applications Up to 10 messages/second/node Time-slotted communications avoids contention. This data rate includes built-in margin for packet retries. Device Features Feature Benefit Industry-Leading Low Power Radio Technology ? 4.5mA to Receive a Packet ? 5.4mA to Transmit at 0dBm ? 9.7mA to Transmit at 8dBm Pre-engineered RF RF elements include an on-chip power amplifier and are pre-tuned for optimized performance, including temperature compensation, saving development time. RF Modular Certifications Pre-certified in USA, Canada, EU, Australia/New Zealand, India, Japan, Korea, Taiwan Energy Harvesting Support Very low power design enables motes to be powered by a wide variety of energy harvesters. Click here to see a demonstration circuit of a SmartMesh IP mote powered by indoor light. Integrated Temperature Sensor Precise temperature sensor is integrated directly into the mote. ApplicationsSmartMesh IP is ideally suited for wireless Industrial Internet of Things (IoT) applications. To learn more about SmartMesh applications, click here.

The ADF7023 is a very low power, high performance, highly integrated 2FSK/GFSK/OOK/MSK/GMSK transceiver designed for operation in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands, which cover the worldwide license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable for circuit applications that operate under the European ETSI EN300-220, the North American FCC (Part 15), the Chinese short-range wireless regulatory standards, or other similar regional standards. Data rates from 1 kbps to 300 kbps are supported.The transmit RF synthesizer contains a VCO and a low noise fractional-N PLL with an output channel frequency resolution of 400 Hz. The VCO operates at 2? or 4?, the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from ?20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allows for Tx antenna diversity.The receiver is exceptionally linear, achieving an IP3 specification of ?12.2 dBm and ?11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at ?2 MHz offset and 74 dB at ?10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, automatic frequency control (AFC) loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet.A patent pending, image rejection calibration scheme is available through a program download. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.See data sheet for additional information.Applications Smart metering IEEE 802.15.4g Wireless MBUS Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare

The ADuCM3027/ADuCM3029 microcontroller units (MCUs) are ultra low power microcontroller systems with integrated power management for processing, control, and connectivity. The MCU system is based on the ARM? Cortex?-M3 processor, a collection of digital peripherals, embedded SRAM and flash memory, and an analog subsystem which provides clocking, reset, and power management capability in addition to an analog-to-digital converter (ADC) subsystem. For a feature comparison across the ADuCM3027/ADuCM3029 product offerings, see Table 1. Table 1. Product Flash Memory Options Device Embedded Flash Memory Size ADuCM3029 256 kB ADuCM3027 128 kB System features that are common across the ADuCM3027/ADuCM3029/ADuCM3029-1/ADuCM3029-2 MCUs include the following: Up to 26 MHz ARM Cortex-M3 processor Up to 256 kB of embedded flash memory with error correction code (ECC) Optional 4 kB cache for lower active power 64 kB system SRAM with parity Power management unit (PMU) Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Beeper interface Serial port (SPORT), serial peripheral interface (SPI), inter-integrated circuit (I2C), and universal asynchronous receiver/transmitter (UART) peripheral interfaces Cryptographic hardware support with advanced encryption standard (AES) and secure hash algorithm (SHA)-256 Real-time clock (RTC) General-purpose and watchdog timers Programmable general-purpose input/output (GPIO) pins Hardware cyclic redundancy check (CRC) calculator with programmable generator polynomial Power-on reset (POR) and power supply monitor (PSM) 12-bit successive approximation register (SAR) ADC True random number generator (TRNG)To support low dynamic and hibernate power management, the ADuCM3027/ADuCM3029 MCUs provide a collection of power modes and features, such as dynamic and software controlled clock gating and power gating.The ADuCM3029-1 and ADuCM3029-2 MCU models share the same features and functionality as that of the ADuCM3029 MCU. All specifications pertaining to the ADuCM3027 and ADuCM3029 are also applicable to the ADuCM3029-1 and ADuCM3029-2.For full details on the ADuCM3027/ADuCM3029 MCUs, refer to the ADuCM302x Ultra Low Power ARM Cortex-M3 MCU with Integrated Power Management Hardware Reference Manual.Product Highlights Industry leading ultralow power consumption. Robust operation, including full voltage monitoring in deep sleep modes, ECC support on flash, and parity error detection on SRAM memory. Leading edge security. Fast encryption provides read protection to customer algorithms. Write protection prevents device reprogramming by unauthorized code. Failure detection of 32 kHz LFXTAL via interrupt. SensorStrobe? for precise time synchronized sampling of external sensors. Works in hibernate mode, resulting in drastic current reduction in system solutions. Current consumption reduces by 10 times when using, for example, the ADXL363 accelerometer. Software intervention is not required after setup. No pulse drift due to software execution.Applications Internet of Things (IoT) Electronic shelf label (ESL) and signage Smart infrastructure Smart lock Asset tracking Smart machine, smart metering, smart building, smart city, and smart agriculture Wearables Fitness and clinical Machine learning and neural network?