BBU DERIVATIVE FOR AD9545 / TRAY ;ROHS COMPLIANT: YES

Clock & Timer Development Tools LTC6994-2 Demo Board 100ms, Output Rising Edge Delayed from Trigger Rising Edge

Clock & Timer Development Tools LTC6992-4 Demo Board - 10kHz, 5-100% Dut

Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC Features: Serial data input: 10 Mbps to 2.7 Gbps Exceeds ITU-T jitter specifications Integrated limiting amplifier 5 mV p-p sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Proprietary dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Integrated PRBS generator and detector No reference clock required Loss of lock indicator Supports double data rate BERMON or sample phase adjust options Rate selectivity without the use of a reference clock I2C interface to access optional features Single-supply operation: 3.3 V Low power 650 mW (ADN2817) 600 mW (ADN2818) 5 mm × 5 mm 32-lead LFCSP

6.2 GHz Fractional-N Frequency Synthesizer Features: RF bandwidth to 6.2 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the ADF4110, ADF4111, ADF4112, ADF4113, ADF4106, ADF4153, and ADF4154 frequency synthesizers Programmable RF output phase Loop filter design possible with ADIsimPLL Cycle slip reduction for faster lock times

Phase-Locked Oscillator SMT, 14.7 - 15.4 GHz Features: Pout: +9 dBm Phase Noise: -110 dBc/Hz @100 KHz Typ. Single Supply: +5V @ 340 mA, 12V @ 28 mA QFN Leadless SMT Package, 16 mm2

CLOCK & TIMING ANALOG DEVELOPMENT KITS;

The ADF41020 frequency synthesizer can be used to implement local oscillators as high as 18 GHz in the up conversion and down conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and high frequency programmable feedback dividers (A, B, and P). A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). The synthesizer can be used to drive external microwave VCOs via an active loop filter. Its very high bandwidth means a frequency doubler stage can be eliminated, simplifying system architecture and reducing cost. The ADF41020 is software-compatible with the existing ADF4106/ADF4107/ADF4108 family of devices from Analog Devices, Inc. Their pinouts match very closely with the exception of the ADF41020’s single-ended RF input pin, meaning only a minor layout change is required when updating current designs.Applications Microwave point-to-point/multipoint radios Wireless infrastructure VSAT radios Test equipment Instrumentation

The AD9522-51 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO.   The AD9522 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V.The AD9522 is specified for operation over the standard industrial range of −40°C to +85°C.The AD9520-5 is an equivalent part to the AD9522-5 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers.1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-5 is used, it is referring to that specific member of the AD9522 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructures

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs.The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device.The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection.This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.APPLICATIONSLow jitter clock distributionClock and data signal restorationLevel translationWireless communicationsWired communicationsMedical and industrial imagingATE and high performance instrumentation