JITTER CLEANER +/PPS + SMALL CELL CLOCK ;ROHS COMPLIANT: YES

EVALUATION BOARD VCO WITH DIVIDE-BY-4; Silicon Manufacturer:Analog Devices; Silicon Core Number:HMC735; Kit Application Type:RF / IF; Application Sub Type:Voltage Controlled Oscillator; Kit Contents:Eval Board HMC735 ;RoHS Compliant: Yes

EVALUATION BOARD VCO WITH DIVIDE-BY-16; Silicon Manufacturer:Analog Devices; Silicon Core Number:HMC739; Kit Application Type:RF / IF; Application Sub Type:Voltage Controlled Oscillator; Kit Contents:Eval Board HMC739 ;RoHS Compliant: Yes

Dual Channel asynchronous evaluation boa ;RoHS Compliant: Yes

EVALUATION BOARD FRACTIONAL-N PLL; Silicon Manufacturer:Analog Devices; Silicon Core Number:HMC834; Kit Application Type:RF / IF; Kit Contents:Eval Board HMC834 USB Interface Board 6ft USB Cable CD ROM; Product Range:- ;RoHS Compliant: Yes

EVALUATION BOARD VCO WITH BUFFER AMP; Silicon Manufacturer:Analog Devices; Silicon Core Number:HMC431; Kit Application Type:RF / IF; Application Sub Type:Voltage Controlled Oscillator; Kit Contents:Eval Board HMC431; Product Range:-;RoHS Compliant: Yes

The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9557 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9557 continuously generates a low jitter output clock even when all reference inputs have failed.The AD9557 operates over an industrial temperature range of −40°C to +85°C. If more inputs/outputs are needed, refer to the AD9558 for the four-input/six-output version of the samedevice.Applications Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping Cleanup of reference clock jitter SONET/SDH/OTN clocks up to 100 Gbps, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Wireless base station controllers Cable infrastructure Data communications

The AD9837 is a low power, programmable waveform generatorcapable of producing sine, triangular, and square wave outputs.Waveform generation is required in various types of sensing,actuation, and time domain reflectometry (TDR) applications. The outputfrequency and phase are software programmable, allowing easytuning. The frequency registers are 28 bits: with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz clock rate, the AD9837can be tuned to 0.02 Hz resolution.The AD9837 is written to via a 3-wire serial interface. This serialinterface operates at clock rates up to 40 MHz and is compatiblewith DSP and microcontroller standards. The device operateswith a power supply from 2.3 V to 5.5 V.The AD9837 has a power-down (SLEEP) function. Sections of the device that are not being used can be powered down to minimize the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated.The AD9837 is available in a 10-lead LFCSP_WD package.APPLICATIONS Frequency stimulus/waveform generation Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Line loss/attenuation Test and medical equipment Sweep/clock generators Time domain reflectometry (TDR) applications

The AD9510 provides a multi-output clock distribution functionalong with an on-chip phase-locked loop (PLL) core. The designemphasizes low jitter and phase noise to maximize data converterperformance. Other applications with demanding phase noiseand jitter requirements also benefit from this device.The PLL section consists of a programmable reference divider(R); a low noise, phase frequency detector (PFD); a precisioncharge pump (CP); and a programmable feedback divider (N).By connecting an external voltage-controlled crystal oscillator(VCXO) or voltage-controlled oscillator (VCO) to the CLK2and CLK2B pins, frequencies of up to 1.6 GHz can be synchronizedto the input reference.There are eight independent clock outputs. Four outputs are lowvoltage positive emitter-coupled logic (LVPECL) at 1.2 GHz,and four are selectable as either LVDS (800 MHz) or CMOS(250 MHz) levels.Each output has a programmable divider that can be bypassedor set to divide by any integer up to 32. The phase of one clockoutput relative to another clock output can be varied by meansof a divider phase select function that serves as a coarse timingadjustment. Two of the LVDS/CMOS outputs feature programmabledelay elements with full-scale ranges up to 8 ns of delay.This fine tuning delay block has 5-bit resolution, giving 25possible delays from which to choose for each full-scale setting(Register 0x36 and Register 0x3A = 00000b to 11000b).The AD9510 is ideally suited for data converter clockingapplications where maximum converter performance isachieved by encode signals with subpicosecond jitter.The AD9510 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. An external VCO, which requires anextended voltage range, can be accommodated by connectingthe charge pump supply (VCP) to 5.5 V. The temperature rangeis −40°C to +85°C.Applications Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and mixed-signal front ends (MxFEs) High performance wireless transceivers High performance instrumentation Broadband infrastructure

The ADF4360-2 is a fully integrated integer-N synthesizerand voltage-controlled oscillator (VCO). The ADF4360-2 isdesigned for a center frequency of 2000 MHz. In addition, adivide-by-2 option is available, whereby the user gets an RFoutput of between 925 MHz and 1085 MHz.Control of all the on-chip registers is through a simple 3-wireinterface. The device operates with a power supply rangingfrom 3.0 V to 3.6 V and can be powered down when not in use.Applications Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment