CLOCK & TIMING ANALOG DEV KITS;

CLOCK & TIMING ANALOG DEV KITS;

CLOCK & TIMING ANALOG DEV KITS;

Timers & Support Products Low-Power General Purpose Timer

EVAL KIT, VOLTAGE CONTROLLED OSCILLATOR;

Delay Lines/Timing Elements Broadband Analog Time Delay to 24 GHz

Real Time Clock Real-Time Event Recorder

Clock & Timer Development Tools LTC6995-2 Demo Board - 1sec Power-on Res

Delay Line IC Nonprogrammable 5 Tap 500ns 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs.The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device.The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection.This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.APPLICATIONSLow jitter clock distributionClock and data signal restorationLevel translationWireless communicationsWired communicationsMedical and industrial imagingATE and high performance instrumentation