CLOCK & TIMING ANALOG DEV KITS;

Timers & Support Products Low-Power General Purpose Timer

EVAL KIT, VOLTAGE CONTROLLED OSCILLATOR;

Delay Lines/Timing Elements Broadband Analog Time Delay to 24 GHz

Real Time Clock Real-Time Event Recorder

Clock & Timer Development Tools LTC6995-2 Demo Board - 1sec Power-on Res

Delay Line IC Nonprogrammable 5 Tap 500ns 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)

The AD9837 is a low power, programmable waveform generatorcapable of producing sine, triangular, and square wave outputs.Waveform generation is required in various types of sensing,actuation, and time domain reflectometry (TDR) applications. The outputfrequency and phase are software programmable, allowing easytuning. The frequency registers are 28 bits: with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz clock rate, the AD9837can be tuned to 0.02 Hz resolution.The AD9837 is written to via a 3-wire serial interface. This serialinterface operates at clock rates up to 40 MHz and is compatiblewith DSP and microcontroller standards. The device operateswith a power supply from 2.3 V to 5.5 V.The AD9837 has a power-down (SLEEP) function. Sections of the device that are not being used can be powered down to minimize the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated.The AD9837 is available in a 10-lead LFCSP_WD package.APPLICATIONS Frequency stimulus/waveform generation Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Line loss/attenuation Test and medical equipment Sweep/clock generators Time domain reflectometry (TDR) applications

Microwave Wideband Synthesizer with Integrated VCO Features: Output frequency range: 800 MHz to 12.8 GHz Jitter = 18 fsRMS (Integration BW: 100 Hz to 100 MHz) Jitter = 27 fsRMS (ADC SNR Method) Wideband Noise Floor: -160 dBc/Hz @12 GHz PLL Specifications: -239 dBc/Hz: Normalized In-Band Phase Noise Floor -147 dBc/Hz: Normalized In-Band 1/f Noise Phase Detector Frequency up to 500 MHzReference Input Frequency up to 1 GHz Typical -100 dBc PFD spursReference to Output Delay Specifications: Part-to-Part Standard Deviation: 3 ps Temperature Drift: 0.03 ps/ Adjustment Step Size: <+/-0.1 ps Multi-chip Output Phase Alignment 3.3 V and 5 V Power supplies 7 mm x 7 mm 48 Lead LGA

Low Phase Noise, Triple Output Clock Distribution Divider/Driver Features: Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking Additive Jitter < 20fsRMS (12kHz to 20MHz) Additive Jitter < 85fsRMS (10Hz to Nyquist) 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0) 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) EZSync™ Clock Synchronization Compatible Three Independent, Low Noise Outputs Four Output Combinations Available Three Independent Programmable Dividers Covering All Integers From 1 to 63 Three Independent Programmable Delays Covering All Integers From 0 to 63 –40°C to 105°C Junction Temperature Range