Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC Features: Serial data input: 10 Mbps to 2.7 Gbps Exceeds ITU-T jitter specifications Integrated limiting amplifier 5 mV p-p sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Proprietary dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Integrated PRBS generator and detector No reference clock required Loss of lock indicator Supports double data rate BERMON or sample phase adjust options Rate selectivity without the use of a reference clock I2C interface to access optional features Single-supply operation: 3.3 V Low power 650 mW (ADN2817) 600 mW (ADN2818) 5 mm × 5 mm 32-lead LFCSP

The LTC6947 is a high performance, low noise, 6GHz phase-locked loop (PLL), including a reference divider, phase-frequency detector (PFD), ultralow noise charge pump, fractional feedback divider, and VCO output divider.The fractional divider uses an advanced, 4th order ?? modulator which provides exceptionally low spurious levels. This allows wide loop bandwidths, producing extremely low integrated phase noise values.The programmable VCO output divider, with a range of 1 through 6, extends the output frequency range. The differential, low-noise output buffer has user-programmable output power ranging from ?4.3dBm to +4.5dBm, and may be muted through either a digital input pin or software.The ultralow noise charge pump contains selectable high and low voltage clamps useful for VCO monitoring, and also may be set to provide a V+/2 bias.All device settings are controlled through a SPI-compatible serial port.Applications Wireless Basestations (LTE, WiMAX, W-CDMA, PCS) Broadband Wireless Access Microwave Data Links Military and Secure Radio Test and Measurement

The LTC6954 is a family of very low phase noise clock distribution parts. Each part has three outputs and each output has an individually programmable frequency divider and delay. There are four members of the family, differing in their output logic signal type:LTC6954-1: Three LVPECL outputsLTC6954-2: Two LVPECL and one LVDS/CMOS outputsLTC6954-3: One LVPECL and two LVDS/CMOS outputsLTC6954-4: Three LVDS/CMOS outputsEach output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output.The LTC6954 also features Linear Technology?s EZSync system for perfect clock synchronization and alignment every time.All device settings are controlled through an SPI-compatible serial port.Applications Clocking High Speed, High Resolution ADCs, DACs?and Data Acquisition Systems Low Jitter Clock Distribution

The LTC6948 is a high performance, low noise, 6.39GHz phase-locked loop (PLL) with a fully integrated VCO, including a reference divider, phase-frequency detector (PFD), ultralow noise charge pump, fractional feedback divider, and VCO output divider.The fractional divider uses an advanced, 4th order ?? modulator which provides exceptionally low spurious levels. This allows wide loop bandwidths, producing extremely low integrated phase noise values.The programmable VCO output divider, with a range of 1 through 6, extends the output frequency range.Applications Wireless Basestations (LTE, WiMAX, W-CDMA, PCS) Microwave Data Links Military and Secure Radio Test and Measurement

The LTC6905 precision, programmable silicon oscillator is easy to use and occupies very little board space. It requires only a single resistor to set the output frequency from 17MHz to 170MHz with a typical frequency error of 0.5% or less.The LTC6905 operates with a single 2.7V to 5.5V power supply and provides a rail-to-rail, 50% duty cycle square wave output. The CMOS output driver ensures fast rise/fall times and rail-to-rail switching. Operation is simple: A single resistor, RSET, between 10K to 25K is used to set the frequency, and an internal three-state divider (DIV input) allows for division of the master clock by 1, 2 or 4, providing three frequencies for each RSET value.The LTC6905 features a proprietary feedback loop that linearizes the relationship between RSET and frequency, eliminating the need for tables to calculate frequency. The oscillator can be easily programmed using the simple formula outlined below:See first page of Data Sheet for formula?For higher accuracy, fixed frequency versions that includean internal frequency-setting resistor, see the LTC6905-XXX Series datasheet.Applications High Frequency Precision Oscillator High Speed Data Bus Clock Fixed Crystal Oscillator Replacement Ceramic Oscillator Replacement

The LTC6900 is a precision, low power oscillator that is easy to use and occupies very little PC board space. The oscillator frequency is programmed by a single external resistor (RSET). The LTC6900 has been designed for high accuracy operation (?1.5% frequency error) without the need for external trim components. The LTC6900 operates with a single 2.7V to 5.5V power supply and provides a rail-to-rail, 50% duty cycle square wave output. The CMOS output driver ensures fast rise/fall times and rail-to-rail switching. The frequency-setting resistor can vary from 10k? to 2M? to select a master oscillator frequency between 100kHz and 20MHz (5V supply). The three-state DIV input determines whether the master clock is divided by 1, 10 or 100 before driving the output, providing three frequency ranges spanning 1kHz to 20MHz (5V supply). The LTC6900 features a proprietary feedback loop that linearizes the relationship between RSET and frequency, eliminating the need for tables to calculate frequency. TApplications Portable and Battery-Powered Equipment PDAs Cell Phones Low Cost Precision Oscillator Charge Pump Driver Switching Power Supply Clock Reference Clocking Switched Capacitor Filters Fixed Crystal Oscillator Replacement Ceramic Oscillator Replacement

Demonstration Circuit 2611A features the LTC6955, Ultralow Jitter 11 Output Fanout Buffers. By default, the DC2611A is powered from a single 3.3V supply. An option is provided to power to the DC2611A from dual supplies, allowing for the LTC6955’s output supply pins to connect to an LTC Silent Switcher® and the LTC6955 input supply pin to connect to a low noise LDO. The differential inputs and six of the differential outputs are populated with 0.5" spaced SMA connectors. These outputs are AC-coupled with 50Ω transmission lines making them suitable to drive 50Ω impedance instruments. All registered trademarks and trademarks are the property of their respective owners. The remaining four differential outputs are terminated with 100Ω. A calibration path is provided to aid in accurate LTC6955 propagation delay measurements. The calibration path can be also reconfigured as a DC path, which allows for a convenient method of locking the LTC6955 outputs to an external PLL/VCO.

The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. The HMC7044 features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs).The DCLK and SYSREF clock outputs of the HMC7044 can be configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses.APPLICATIONS JESD204B clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Microwave baseband cards Phase array reference distribution

DC1446A: Demo Board for the LTC6909 1 to 8 Output, Multiphase Silicon Oscillator with Spread Spectrum Modulation.

Demonstration circuit 1562B is an engineering tool to design and evaluate the LTC699X-X family of TimerBlox® circuits. The center section of the board contains a preconfigured TimerBlox function. DC1562B comes in twelve timing function variations as outlined in Table 1.