EVALUATION BOARD FRACTIONAL-N PLL; Silicon Manufacturer:Analog Devices; Silicon Core Number:HMC834; Kit Application Type:RF / IF; Kit Contents:Eval Board HMC834 USB Interface Board 6ft USB Cable CD ROM; Product Range:- ;RoHS Compliant: Yes

EVALUATION BOARD VCO WITH BUFFER AMP; Silicon Manufacturer:Analog Devices; Silicon Core Number:HMC431; Kit Application Type:RF / IF; Application Sub Type:Voltage Controlled Oscillator; Kit Contents:Eval Board HMC431; Product Range:-;RoHS Compliant: Yes

EVALUATION BOARD VCO WITH DIVIDE-BY-16; Silicon Manufacturer:Analog Devices; Silicon Core Number:HMC739; Kit Application Type:RF / IF; Application Sub Type:Voltage Controlled Oscillator; Kit Contents:Eval Board HMC739 ;RoHS Compliant: Yes

EVALUATION BOARD VCO WITH DIVIDE-BY-4; Silicon Manufacturer:Analog Devices; Silicon Core Number:HMC735; Kit Application Type:RF / IF; Application Sub Type:Voltage Controlled Oscillator; Kit Contents:Eval Board HMC735 ;RoHS Compliant: Yes

JITTER CLEANER +/PPS + SMALL CELL CLOCK ;ROHS COMPLIANT: YES

Dual Channel asynchronous evaluation boa ;RoHS Compliant: Yes

BBU DERIVATIVE FOR AD9545 / TRAY ;ROHS COMPLIANT: YES

Together with an external loop filter and a voltage controlled crystal oscillator (VCXO), the HMC1031 forms a complete clock generator solution targeted at low frequency jitter attenuation and reference clock generation applications.The HMC1031 features a low power integer N divider, support-ing divide ratios of 1, 5, and 10, which is controlled via external hardware pins and requires no serial port.The integrated phase detector and charge pump are capable of operating at up to 140 MHz, and a maximum VCXO input of 500 MHz ensures frequency compliance with a wide variety of system clocks and VCXOs.Additional features include an integrated lock detect indicator available on a dedicated hardware pin, and a built in power-down mode.The HMC1031 is housed in an 8-lead MSOP package.APPLICATIONS Low jitter clock generation Low bandwidth (BW) jitter attenuation Low frequency phase-locked loops PLL Frequency translation Oven controlled crystal oscillator (OCXO) frequency multiplier Phase lock clean high frequency references to 10 MHz equipment

Clock & Timer Development Tools LTC6994-2 Demo Board 100ms, Output Rising Edge Delayed from Trigger Rising Edge

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.The AD9559 operates over an industrial temperature range of ?40?C to +85?C. If a single DPLL version of this part is needed, refer to the AD9557.APPLICATIONS Network synchronization, including Synchronous Ethernet and OTN mapping/de-mapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Wireless base station controllers Cable infrastructure Data communications