Clock & Timer Development Tools LTC6994-2 Demo Board 100ms, Output Rising Edge Delayed from Trigger Rising Edge

Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC Features: Serial data input: 10 Mbps to 2.7 Gbps Exceeds ITU-T jitter specifications Integrated limiting amplifier 5 mV p-p sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Proprietary dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Integrated PRBS generator and detector No reference clock required Loss of lock indicator Supports double data rate BERMON or sample phase adjust options Rate selectivity without the use of a reference clock I2C interface to access optional features Single-supply operation: 3.3 V Low power 650 mW (ADN2817) 600 mW (ADN2818) 5 mm × 5 mm 32-lead LFCSP

6.2 GHz Fractional-N Frequency Synthesizer Features: RF bandwidth to 6.2 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the ADF4110, ADF4111, ADF4112, ADF4113, ADF4106, ADF4153, and ADF4154 frequency synthesizers Programmable RF output phase Loop filter design possible with ADIsimPLL Cycle slip reduction for faster lock times

Low Phase Noise, Triple Output Clock Distribution Divider/Driver Features: Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking Additive Jitter < 20fsRMS (12kHz to 20MHz) Additive Jitter < 85fsRMS (10Hz to Nyquist) 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0) 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) EZSync™ Clock Synchronization Compatible Three Independent, Low Noise Outputs Four Output Combinations Available Three Independent Programmable Dividers Covering All Integers From 1 to 63 Three Independent Programmable Delays Covering All Integers From 0 to 63 –40°C to 105°C Junction Temperature Range

Phase-Locked Oscillator SMT, 14.7 - 15.4 GHz Features: Pout: +9 dBm Phase Noise: -110 dBc/Hz @100 KHz Typ. Single Supply: +5V @ 340 mA, 12V @ 28 mA QFN Leadless SMT Package, 16 mm2

Dual DPLL, Quad Input, 10 Output, Multiservice Line Card Clock Translator and Jitter Cleaner Features:Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppbBoth DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 104 Hz to 1850 HzAutomatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 4 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor/alarm and temperature compensation for enhanced zero delay performance

Microwave Wideband Synthesizer with Integrated VCO Features: Output frequency range: 800 MHz to 12.8 GHz Jitter = 18 fsRMS (Integration BW: 100 Hz to 100 MHz) Jitter = 27 fsRMS (ADC SNR Method) Wideband Noise Floor: -160 dBc/Hz @12 GHz PLL Specifications: -239 dBc/Hz: Normalized In-Band Phase Noise Floor -147 dBc/Hz: Normalized In-Band 1/f Noise Phase Detector Frequency up to 500 MHzReference Input Frequency up to 1 GHz Typical -100 dBc PFD spursReference to Output Delay Specifications: Part-to-Part Standard Deviation: 3 ps Temperature Drift: 0.03 ps/ Adjustment Step Size: <+/-0.1 ps Multi-chip Output Phase Alignment 3.3 V and 5 V Power supplies 7 mm x 7 mm 48 Lead LGA

CLOCK & TIMING ANALOG DEVELOPMENT KITS;

CLOCK GENERATORS & BUFFERS;

CLOCK & TIMING ANALOG DEV KITS;