The HMC835LP6GE is a low noise, wide band, Fractional-N PLL that features an integrated VCO with a fundamental frequency of 2020 to 4100 MHz, and an integrated VCO Output Divider (divide by 2/4/6/.../60/62) that together enable the HMC835LP6GE to generate frequencies from 33 MHz to 4100 MHz. Integrated Phase Detector (PD) and a deltasigma modulator capable of operating at up to 100 MHz enable wider loop-bandwidths, faster frequency changes along with excellent spectral performance.Two independent RF outputs, with independent gain control, enable the HMC835LP6GE to distribute identical frequency and phase signals to multiple destinations, at optimal signal levels tailored to each output.External VCO input, allows the HMC835LP6GE to lock external VCOs, and enables cascaded LO architectures for MIMO radio applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both integrated and external VCOs, and seamless switching between integrated or external VCOs during operation. Programmable RF output phase feature can further phase adjust and synchronize multiple HMC835LP6GEs enabling scalable MIMO and beam-forming radio architectures.Additional features include configurable output mute function that mutes RF outputs during frequency changes, Exact Frequency Mode that enables the HMC835LP6GE to generate fractional frequencies with 0 Hz frequency error, and the ability to synchronously change frequencies without changing the phase of the output signal.Applications MIMO Radio Architectures Cellular Infrastructure Cellular backhaul Communications Test Equipment CATV Equipment Phased Array Applications? DDS Replacement

The ADF5000 prescaler is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input to a PLL IC, such as the?ADF4156 or the ADF4106. The ADF5000 provides a divide-by-2 function. The ADF5000 operates from a 3.3 V supply and has differential 100 ? RF outputs to allow direct interface to the differential RF inputs of PLLs such as the ADF4156 and ADF4106.Applications PLL frequency range extender Point-to-point radios VSAT radios Communications test equipment?

The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. The HMC7044 features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs).The DCLK and SYSREF clock outputs of the HMC7044 can be configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses.APPLICATIONS JESD204B clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Microwave baseband cards Phase array reference distribution

The HMC833LP6GE is a low noise, wide band, Fractional-N Phase-Locked-Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO) with a fundamental frequency of 1500 MHz - 3000 MHz, and an integrated VCO Output Divider (divide by 1/2/4/6.../60/62) and doubler, that together allow the HMC833LP6GE to generate frequencies from 25 MHz to 6000 MHz. The integrated Phase Detector (PD) and delta-sigma modulator, capable of operating at up to 100 MHz, permit wider loop-bandwidths with excellent spectral performance.The HMC833LP6GE features industry leading phase noise and spurious performance, across all frequencies, that enable it to minimize blocker effects, and improve receiver sensitivity and transmitter spectral purity. The superior noise floor (< -170 dBc/Hz) makes the HMC833LP6GE an ideal source for a variety of applications - such as; LO for RF mixers, a clock source for high-frequency data-converters, or a tunable reference source for ultra-low spurious applications.Additional features of the HMC833LP6GE include RF output power control from 0 to 9 dB (3 dB steps), output Mute function, and a delta-sigma modulator Exact Frequency Mode which enables users to generate output frequencies with 0 Hz frequency error.Applications Cellular Infrastructure Microwave Radio WiMax, WiFi Communications Test Equipment CATV Equipment DDS Replacement Military Tunable Reference Source for?Spurious- Free Performance

The HMC835LP6GE is a low noise, wide band, Fractional-N PLL that features an integrated VCO with a fundamental frequency of 2020 to 4100 MHz, and an integrated VCO Output Divider (divide by 2/4/6/.../60/62) that together enable the HMC835LP6GE to generate frequencies from 33 MHz to 4100 MHz. Integrated Phase Detector (PD) and a deltasigma modulator capable of operating at up to 100 MHz enable wider loop-bandwidths, faster frequency changes along with excellent spectral performance.Two independent RF outputs, with independent gain control, enable the HMC835LP6GE to distribute identical frequency and phase signals to multiple destinations, at optimal signal levels tailored to each output.External VCO input, allows the HMC835LP6GE to lock external VCOs, and enables cascaded LO architectures for MIMO radio applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both integrated and external VCOs, and seamless switching between integrated or external VCOs during operation. Programmable RF output phase feature can further phase adjust and synchronize multiple HMC835LP6GEs enabling scalable MIMO and beam-forming radio architectures.Additional features include configurable output mute function that mutes RF outputs during frequency changes, Exact Frequency Mode that enables the HMC835LP6GE to generate fractional frequencies with 0 Hz frequency error, and the ability to synchronously change frequencies without changing the phase of the output signal.Applications MIMO Radio Architectures Cellular Infrastructure Cellular backhaul Communications Test Equipment CATV Equipment Phased Array Applications? DDS Replacement

The HMC1162 is a monolithic microwave integrated circuit (MMIC), voltage controlled oscillator (VCO) that integrates the resonator, a negative resistance device, and varactor diodes, and features a half frequency output.Because of the monolithic construction of the oscillator, the output power and phase noise performance are excellent over temperature.The power output is 11 dBm typical from a 5 V supply voltage. The VCO is housed in a RoHS-compliant, 32-lead LFCSP and requires no external matching components.APPLICATIONS Point to point and multipoint radios Test equipment and industrial controls Very small aperture terminals (VSATs)

The HMC832A is a 3.3 V, high performance, wideband, fractional-N, phase-locked loop (PLL) that features an integrated voltage controlled oscillator (VCO) with a fundamental frequency of 1500 MHz to 3000 MHz and an integrated VCO output divider (divide by 1, 2, 4, 6, ? 62) that enables the HMC832A to generate continuous frequencies from 25 MHz to 3000 MHz. The integrated phase detector (PD) and ?-? modulator, capable of operating at up to 100 MHz, permit wider loop bandwidths and faster frequency tuning with excellent spectral performance.Industry leading phase noise and spurious performance, across all frequencies, enable the HMC832A to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. A low noise floor (?160 dBc/Hz) eliminates any contribution to modulator/mixer noise floor in transmitter applications.The HMC832A is footprint compatible to the market leading HMC830 PLL with an integrated VCO. It features 3.3 V supply and an innovative programmable performance technology that enables the HMC832A to tailor current consumption and corresponding noise floor performance to individual applications by selecting either a low current consumption mode or a high performance mode for an improved noise floor performance.Additional features of the HMC832A include 12 dB of RF output gain control in 1 dB steps; an output mute function to automatically mute the output during frequency changes when the device is not locked; selectable output return loss; programmable differential or single-ended outputs, with the ability to select either output in single-ended mode; and a ?-? modulator exact frequency mode that enables users to generate output frequencies with 0 Hz frequency error; and a register configurable 3.3 V or 1.8 V serial port interface (SPI).Applications Cellular infrastructure Microwave radios WiMax, WiFi Communications test equipment CATV equipment DDS replacement Military Tunable reference sources for spurious-free performance

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The ADF4153A is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. A sigma-delta (?-?) based fractional interpolator allows programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO).A simple 3-wire interface controls all on-chip registers. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.Applications CATV equipment Base stations for mobile radio (GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA, W-CDMA) Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA) Wireless LANs, PMR Communications test equipment

Demonstration Circuit 2611A features the LTC6955, Ultralow Jitter 11 Output Fanout Buffers. By default, the DC2611A is powered from a single 3.3V supply. An option is provided to power to the DC2611A from dual supplies, allowing for the LTC6955’s output supply pins to connect to an LTC Silent Switcher® and the LTC6955 input supply pin to connect to a low noise LDO. The differential inputs and six of the differential outputs are populated with 0.5" spaced SMA connectors. These outputs are AC-coupled with 50Ω transmission lines making them suitable to drive 50Ω impedance instruments. All registered trademarks and trademarks are the property of their respective owners. The remaining four differential outputs are terminated with 100Ω. A calibration path is provided to aid in accurate LTC6955 propagation delay measurements. The calibration path can be also reconfigured as a DC path, which allows for a convenient method of locking the LTC6955 outputs to an external PLL/VCO.