Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC Features: Serial data input: 10 Mbps to 2.7 Gbps Exceeds ITU-T jitter specifications Integrated limiting amplifier 5 mV p-p sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Proprietary dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Integrated PRBS generator and detector No reference clock required Loss of lock indicator Supports double data rate BERMON or sample phase adjust options Rate selectivity without the use of a reference clock I2C interface to access optional features Single-supply operation: 3.3 V Low power 650 mW (ADN2817) 600 mW (ADN2818) 5 mm × 5 mm 32-lead LFCSP

CLOCK & TIMING ANALOG DEVELOPMENT KITS;

CLOCK GENERATORS & BUFFERS;

CLOCK & TIMING ANALOG DEV KITS;

CLOCK & TIMING ANALOG DEV KITS;

Dual DPLL, Quad Input, 10 Output, Multiservice Line Card Clock Translator and Jitter Cleaner Features:Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppbBoth DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 104 Hz to 1850 HzAutomatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 4 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor/alarm and temperature compensation for enhanced zero delay performance

Clock & Timer Development Tools HMC7043LP7FE EVAL KIT

The AD9510 provides a multi-output clock distribution functionalong with an on-chip phase-locked loop (PLL) core. The designemphasizes low jitter and phase noise to maximize data converterperformance. Other applications with demanding phase noiseand jitter requirements also benefit from this device.The PLL section consists of a programmable reference divider(R); a low noise, phase frequency detector (PFD); a precisioncharge pump (CP); and a programmable feedback divider (N).By connecting an external voltage-controlled crystal oscillator(VCXO) or voltage-controlled oscillator (VCO) to the CLK2and CLK2B pins, frequencies of up to 1.6 GHz can be synchronizedto the input reference.There are eight independent clock outputs. Four outputs are lowvoltage positive emitter-coupled logic (LVPECL) at 1.2 GHz,and four are selectable as either LVDS (800 MHz) or CMOS(250 MHz) levels.Each output has a programmable divider that can be bypassedor set to divide by any integer up to 32. The phase of one clockoutput relative to another clock output can be varied by meansof a divider phase select function that serves as a coarse timingadjustment. Two of the LVDS/CMOS outputs feature programmabledelay elements with full-scale ranges up to 8 ns of delay.This fine tuning delay block has 5-bit resolution, giving 25possible delays from which to choose for each full-scale setting(Register 0x36 and Register 0x3A = 00000b to 11000b).The AD9510 is ideally suited for data converter clockingapplications where maximum converter performance isachieved by encode signals with subpicosecond jitter.The AD9510 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. An external VCO, which requires anextended voltage range, can be accommodated by connectingthe charge pump supply (VCP) to 5.5 V. The temperature rangeis −40°C to +85°C.Applications Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and mixed-signal front ends (MxFEs) High performance wireless transceivers High performance instrumentation Broadband infrastructure

The LTC6951 is a high performance, low noise, Phase Locked Loop (PLL) with a fully integrated VCO. The low noise VCO uses no external components and is internally calibrated to the correct output frequency with no external system support.The clock generation section provides five outputs based on the VCO prescaler signal with individual dividers for each output. Four outputs feature very low noise, low skew CML logic. The fifth output is low noise LVDS. All outputs can be synchronized and set to precise phase alignment using the programmable delays.Choose the LTC6951-1 if any desired output frequency falls in the ranges 2.5GHz to 2.7GHz, 1.66GHz to 1.8GHz, or 1.25GHz to 1.35GHz. Choose the LTC6951 for all other frequencies.Applications High Performance Data Converter Clocking Wireless Infrastructure Test and Measurement

The HMC1165 is a monolithic microwave integrated circuit (MMIC), voltage controlled oscillator (VCO) that integrates a resonator, a negative resistance device, and a varactor diode, and features a half frequency output. Because of the monolithic construction of the oscillator, the output power and phase noise performance are excellent over temperature.The output power is 8 dBm typical from a 5 V supply voltage. The VCO is housed in a RoHS-compliant LFCSP and requires no external matching components.Applications Point to point and multipoint radios  Test equipment and industrial controls  Very small aperture terminals (VSATs)