Low Phase Noise, Triple Output Clock Distribution Divider/Driver Features: Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking Additive Jitter < 20fsRMS (12kHz to 20MHz) Additive Jitter < 85fsRMS (10Hz to Nyquist) 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0) 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) EZSync™ Clock Synchronization Compatible Three Independent, Low Noise Outputs Four Output Combinations Available Three Independent Programmable Dividers Covering All Integers From 1 to 63 Three Independent Programmable Delays Covering All Integers From 0 to 63 –40°C to 105°C Junction Temperature Range

Dual DPLL, Quad Input, 10 Output, Multiservice Line Card Clock Translator and Jitter Cleaner Features:Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppbBoth DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 104 Hz to 1850 HzAutomatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 4 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor/alarm and temperature compensation for enhanced zero delay performance

CLOCK & TIMING ANALOG DEVELOPMENT KITS;

CLOCK GENERATORS & BUFFERS;

CLOCK & TIMING ANALOG DEV KITS;

CLOCK & TIMING ANALOG DEV KITS;

CLOCK & TIMING ANALOG DEV KITS;

IC/CLK FANOUT BUFFER, 2.97V-3.63V, LFCSP ROHS COMPLIANT: YES

Clock & Timer Development Tools HMC7043LP7FE EVAL KIT

The ADF41020 frequency synthesizer can be used to implement local oscillators as high as 18 GHz in the up conversion and down conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and high frequency programmable feedback dividers (A, B, and P). A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). The synthesizer can be used to drive external microwave VCOs via an active loop filter. Its very high bandwidth means a frequency doubler stage can be eliminated, simplifying system architecture and reducing cost. The ADF41020 is software-compatible with the existing ADF4106/ADF4107/ADF4108 family of devices from Analog Devices, Inc. Their pinouts match very closely with the exception of the ADF41020’s single-ended RF input pin, meaning only a minor layout change is required when updating current designs.Applications Microwave point-to-point/multipoint radios Wireless infrastructure VSAT radios Test equipment Instrumentation