The HMC513LP5(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCOs. The HMC513LP5(E) integrates resonators, negative resistance devices, varactor diodes and feature half frequency and divide-by- 4 outputs. The VCO’s phase noise performance is excellent over temperature, shock, and process due to the oscillator’s monolithic structure. Power output is +7 dBm typical from a +3V supply voltage. The prescaler function can be disabled to conserve current if not required. The voltage controlled oscillator is packaged in a leadless QFN 5×5 mm surface mount package, and requires no external matching components.APPLICATIONS VSAT Radio Point-to-Point/Multi-Point Radio  Test Equipment & Industrial Controls  Military End-Use

The HMC515LP5(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO. The HMC515LP5(E) integrates resonators, negative resistance devices, varactor diodes and feature half frequency and divide-by-4 outputs. The VCO’s phase noise performance is excellent over temperature, shock, and process due to the oscillator’s monolithic structure. Power output is +10 dBm typical from a +5V supply voltage. The prescaler function can be disabled to conserve current if not required. The voltage controlled oscillator is packaged in a leadless QFN 5x5 mm surface mount package, and requires no external matching components.APPLICATIONS VSAT Radio  Point-to-Point/Multi-Point Radio  Test Equipment & Industrial Controls  Military End-Use

The ADF4368 is a high performance, ultralow jitter, integer-N and fractional-N phase-locked loop (PLL) with integrated VCO ideally suited for frequency conversion applications.The high performance PLL has a figure of merit of -239dBc/Hz, very low 1/f Noise of normalized -287dBc/Hz and high PFD frequency that can achieve ultralow in-band noise and integrated jitter. The ADF4368 can generate any frequency from 800 MHz to 12.8 GHz without an internal doubler, thereby eliminating the need for sub-harmonic filters. Σ-Δ modulator includes a 25-bit fixed modulus which allows hertz frequency resolution and an additional 24-bit variable modulus which allows even finer resolution and flexibility for frequency planning. 9 dBm output power at 12.8 GHz in single ended configuration with 16 step power adjust feature makes it very useful for any application.For multiple frequency conversion applications such as phase array radar or massive MIMO systems, the outputs of multiple ADF4368 can be aligned by using SYNC input or EZSync. EZSync method is used when it is difficult to distribute the SYNC signal to all parts precisely. For applications that require deterministic delay or delay adjustment capability, a programmable reference to output delay with The simplicity of the ADF4368 block diagram eases development time with a simplified SPI register map, external SYNC input and repeatable multi-chip phase alignment both in integer and fractional mode.APPLICATIONSWireless infrastructure (MC-GSM, 5G)Test and MeasurementAerospace and Defense

The HMC582LP5(E) is a GaAs InGaP Herterojunction Bipolar Transistor (HBT) MMIC VCOs. The HMC582LP5(E) integrates resonators, negative resistance devices, varactor diodes and feature half frequency and divide-by-4 outputs. The VCO's phase noise performance is excellent over temperature, shock and process due to the oscillator's monolithic structure.Power output is +9 dBm typical from a +5V supply voltage. The prescaler and RF/2 functions can be disabled to conserve current if not required. The voltage controlled oscillator is packaged in a leadless QFN 5×5 mm surface mount package, and requires no external matching components.APPLICATIONS Point-to-Point Radios Point-to-Multi-Point Radios Test Equipment & Industrial Controls SATCOM Military End-Use

Low Phase Noise, Triple Output Clock Distribution Divider/Driver Features: Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking Additive Jitter < 20fsRMS (12kHz to 20MHz) Additive Jitter < 85fsRMS (10Hz to Nyquist) 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0) 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) EZSync™ Clock Synchronization Compatible Three Independent, Low Noise Outputs Four Output Combinations Available Three Independent Programmable Dividers Covering All Integers From 1 to 63 Three Independent Programmable Delays Covering All Integers From 0 to 63 –40°C to 105°C Junction Temperature Range

Dual DPLL, Quad Input, 10 Output, Multiservice Line Card Clock Translator and Jitter Cleaner Features:Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppbBoth DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 104 Hz to 1850 HzAutomatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 4 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor/alarm and temperature compensation for enhanced zero delay performance

Microwave Wideband Synthesizer with Integrated VCO Features: Output frequency range: 800 MHz to 12.8 GHz Jitter = 18 fsRMS (Integration BW: 100 Hz to 100 MHz) Jitter = 27 fsRMS (ADC SNR Method) Wideband Noise Floor: -160 dBc/Hz @12 GHz PLL Specifications: -239 dBc/Hz: Normalized In-Band Phase Noise Floor -147 dBc/Hz: Normalized In-Band 1/f Noise Phase Detector Frequency up to 500 MHzReference Input Frequency up to 1 GHz Typical -100 dBc PFD spursReference to Output Delay Specifications: Part-to-Part Standard Deviation: 3 ps Temperature Drift: 0.03 ps/ Adjustment Step Size: <+/-0.1 ps Multi-chip Output Phase Alignment 3.3 V and 5 V Power supplies 7 mm x 7 mm 48 Lead LGA

Clock & Timer Development Tools LTC6995-2 Demo Board - 1sec Power-on Res

Phase-Locked Oscillator SMT, 14.7 - 15.4 GHz Features: Pout: +9 dBm Phase Noise: -110 dBc/Hz @100 KHz Typ. Single Supply: +5V @ 340 mA, 12V @ 28 mA QFN Leadless SMT Package, 16 mm2

IC/CLK FANOUT BUFFER, 2.97V-3.63V, LFCSP ROHS COMPLIANT: YES