IC/CLK FANOUT BUFFER, 2.97V-3.63V, LFCSP ROHS COMPLIANT: YES

Clock & Timer Development Tools HMC7043LP7FE EVAL KIT

CLOCK & TIMING ANALOG DEV KITS;

CLOCK & TIMING ANALOG DEV KITS;

CLOCK & TIMING ANALOG DEV KITS;

Clock & Timer Development Tools LTC6992-4 Demo Board - 10kHz, 5-100% Dut

The AD9510 provides a multi-output clock distribution functionalong with an on-chip phase-locked loop (PLL) core. The designemphasizes low jitter and phase noise to maximize data converterperformance. Other applications with demanding phase noiseand jitter requirements also benefit from this device.The PLL section consists of a programmable reference divider(R); a low noise, phase frequency detector (PFD); a precisioncharge pump (CP); and a programmable feedback divider (N).By connecting an external voltage-controlled crystal oscillator(VCXO) or voltage-controlled oscillator (VCO) to the CLK2and CLK2B pins, frequencies of up to 1.6 GHz can be synchronizedto the input reference.There are eight independent clock outputs. Four outputs are lowvoltage positive emitter-coupled logic (LVPECL) at 1.2 GHz,and four are selectable as either LVDS (800 MHz) or CMOS(250 MHz) levels.Each output has a programmable divider that can be bypassedor set to divide by any integer up to 32. The phase of one clockoutput relative to another clock output can be varied by meansof a divider phase select function that serves as a coarse timingadjustment. Two of the LVDS/CMOS outputs feature programmabledelay elements with full-scale ranges up to 8 ns of delay.This fine tuning delay block has 5-bit resolution, giving 25possible delays from which to choose for each full-scale setting(Register 0x36 and Register 0x3A = 00000b to 11000b).The AD9510 is ideally suited for data converter clockingapplications where maximum converter performance isachieved by encode signals with subpicosecond jitter.The AD9510 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. An external VCO, which requires anextended voltage range, can be accommodated by connectingthe charge pump supply (VCP) to 5.5 V. The temperature rangeis −40°C to +85°C.Applications Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and mixed-signal front ends (MxFEs) High performance wireless transceivers High performance instrumentation Broadband infrastructure

The ADF4360-2 is a fully integrated integer-N synthesizerand voltage-controlled oscillator (VCO). The ADF4360-2 isdesigned for a center frequency of 2000 MHz. In addition, adivide-by-2 option is available, whereby the user gets an RFoutput of between 925 MHz and 1085 MHz.Control of all the on-chip registers is through a simple 3-wireinterface. The device operates with a power supply rangingfrom 3.0 V to 3.6 V and can be powered down when not in use.Applications Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs.The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device.The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection.This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.APPLICATIONSLow jitter clock distributionClock and data signal restorationLevel translationWireless communicationsWired communicationsMedical and industrial imagingATE and high performance instrumentation

The ADCLK948 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs. The ADCLK948 features eight full-swing emitter coupled logic(ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.The output stages are designed to directly drive 800 mV eachside into 50 Ω terminated to VCC -2V for a total differential output swing of 1.6V. The ADCLK948 is available in a 32-lead LFCSP and specified for operation over the standard industrial temperature range of −40°C to +85°C.APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation