ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial, Parallel, Word Access, CMOS, PDSO24

Dual Low Power, 8-Bit TxDAC Digital-to-Analog Converters Features:Power dissipation @ 3.3 V, 20 mA output191 mW @ 10 MSPS 232 mW @ 125 MSPSSleep mode: Supply voltage: 1.8 V to 3.3 VSFDR to Nyquist86 dBc @ 1 MHz output 85 dBc @ 10 MHz outputNSD @ 10 MHz output, 125 MSPS, 20 mA: 132 dBc/Hz Differential current outputs: 4 mA to 20 mA2 on-chip auxiliary DACsCMOS inputs with single-port operationOutput common mode: adjustable 0 V to 1.2 VSmall footprint 40-lead LFCSP RoHS-compliant package

24-Bit, 8.5 mW, 109 dB, 128 kSPS/64 kSPS/32 kSPS ADCs Features: Download AD7766-2-KGD Data Sheet. Available as Known Good Die and fully guaranteed in data sheet specifications Oversampled successive approximation (SAR) architecture High performance ac and dc accuracy, low power 115.5 dB dynamic range, 32 kSPS (AD7766-2) 112.5 dB dynamic range, 64 kSPS (AD7766-1) 109.5 dB dynamic range, 128 kSPS (AD7766) −112 dB THD Exceptionally low power 8.5 mW, 32 kSPS (AD7766-2) 10.5 mW, 64 kSPS (AD7766-1) 15 mW, 128 kSPS (AD7766) High dc accuracy 24 bits, no missing codes (NMC) INL: ±6 ppm (typical), ±15 ppm (maximum) Low temperature drift Zero error drift: 15 nV/°C Gain error drift: 0.4 ppm/°C See data sheet for additional features

2.5 V to 5.5 V, 500 A, Quad Voltage Output 10-Bit DAC in 10-Lead Packages Features: 4 buffered 10-Bit DACs in 10-lead MSOP and 10-lead LFCSP A, W Version: ±4 LSB INL, B Version: ±2.5 LSB INL Low power operation: 500 µA @ 3 V, 600 µA @ 5 V 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 80 nA @ 3 V, 200 nA @ 5 V Double-buffered input logic Output range: 0 V to VREF Power-on reset to 0 V Simultaneous update of outputs (LDAC function) Low power-, SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible 3-wire serial interface On-chip, rail-to-rail output buffer amplifiers Temperature range –40°C to +105°C Qualified for automotive applications

LC2MOS 16-Bit Voltage Output DAC Features: 16-bit monotonicity over temperature ±2 LSBs integral linearity error Microprocessor compatible with readback capability Unipolar or bipolar output Multiplying capability Low power (100 mW typical)

Software Selectable, True Bipolar Input, 8-Channel, 12-Bit Plus Sign A/D Converter Features: 12-Bit plus Sign SAR ADC True Bipolar Input Ranges Software Selectable Input Ranges: ± 10V, ± 5V, ± 2.5V, 0 to 10V Eight Analog Input Channels with Channel Sequencer Single Ended, True Differential and Pseudo Differential Analog Input Capability High Analog Input Impedance Low Power: 26 mW Full Power Signal Bandwidth: >13 MHz Internal 2.5 V Reference High Speed Serial Interface - 1 MSPS Throughput For four and two channel equivalent devices, see AD7324, AD7322

24-Bit, 312 kSPS, 109 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface Features: High performance 24-bit Σ-Δ ADC 115 dB dynamic range at 78.125 kHz output data rate 109 dB dynamic range at 312.5 kHz output data rate 312.5 kHz maximum fully filtered output word rate Pin-selectable oversampling rates of 64×, 128×, and 256× Low power mode Flexible serial peripheral interface (SPI) Fully differential modulator input On-chip differential amplifier for signal buffering On-chip reference buffer Full band, low-pass, finite impulse response (FIR) filter Overrange alert pin Digital gain correction registers Power-down mode Synchronization of multiple devices via the SYNC pin Daisy chaining

500 kSPS, 2-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC Features: 12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges: ±10 V, ±5 V, ±2.5 V, 0 V to +10 V 2 analog input channels with channel sequencer Single-ended, true differential, and pseudo differential analog input capability 500 kSPS throughput rate High analog input impedance Low power: 18 mW Full power signal bandwidth: 22 MHz Internal 2.5 V reference High speed serial interface See data sheet for additional features

Dual, 12-Bit, 80 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter Features: 1.8 V supply operation Low power: 115 mW per channel at 125 MSPS with scalable power options SNR = 71 dBFS (to Nyquist) SFDR = 93 dBc at 70 MHz DNL = −0.1 LSB to +0.2 LSB (typical); INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) and low power, reduced range option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input voltage range Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Clock divider Programmable output clock and data alignment Programmable output resolution Standby mode

Quad 14-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface Features: High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range