14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Data output clock and clock duty cycle stabilizer Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) See data sheet for additional features

8-Bit, 50 MSPS/80 MSPS/100 MSPS ADC Features: Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth 46.5 dB SNR at 100 MSPS with 41 MHz input 1 Vp-p Analog Input Range Single +3.0 V Supply Operation (2.7 -3.6 V) Power Down Mode: 4.2 mW

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Features: 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply SNR 82 dBFS at 30 MHz input and 105 MSPS data rate 83 dBFS at 9.7 MHz input and 25 MSPS data rate SFDR 90 dBc at 30 MHz input and 105 MSPS data rate 95 dBc at 9.7 MHz input and 25 MSPS data rate Low power 328 mW per channel at 105 MSPS 119 mW per channel at 25 MSPS Integer 1-to-8 input clock divider See data sheet for additional featuresAD9650-EP supports defense and aerospace applications (AQEC standard) Download AD9650-EP data sheet (pdf)

10-Bit, 100 MSPS+ TxDAC D/A Converter Features: Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs: 2 ma to 20 mA Edge-Triggered Latches See datasheet for additional features

16-Bit 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+ D/A Converter Features: 16-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment fS/4, fS/8 digital quadrature modulation capability Fully compatible SPI® port Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture See datasheet for additional features

Dual, 12-Bit, 1 GSPS, Digital-to-Analog Converter Features: Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP

Broadband Modem Mixed-Signal Front End Features: Low cost, 3.3 V CMOS MxFE® for broadband modems 10-bit digital-to-analog converter (DAC) 2×/4× interpolation filter 250 MSPS DAC update rate 10-bit, 75 MSPS ADC Low noise RxPGA Dual channel muxed input 6 dB input overload attenuator −12 dB to +48 dB (without attenuator) Third-order programmable low-pass filter Flexible digital datapath interface Half-duplex and full-duplex operation Programmable delay Tx driver disable signal Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs 64-lead LFCSP

Robust, Triple Ch. Isolator W/ Output Enable & 0 Reverse Channels Features: High common-mode transient immunity: 100 kV/µs High robustness to radiated and conducted noise Low propagation delay 13 ns maximum for 5 V operation 15 ns maximum for 1.8 V operation 150 Mbps maximum guaranteed data rate Backward compatibility ADuM130E1/ADuM131E1 pin compatible with ADuM1300/ADUM1301 Low dynamic power consumption 1.8 V to 5 V level translation High temperature operation: 125°C Fail-safe high or low options 16-lead, RoHS compliant, SOIC package See data sheet for additional information