Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Low Power, 5-Electrode Electrocardiogram (ECG) Analog Front End with respiration measurement and pace detection) Features: Biopotential signals in; digitized signals out 5 acquisition (ECG) channels and one driven lead Parallel ICs for up to 10+ electrode measurements Master ADAS1000 or ADAS1000-1 used with slave ADAS1000-2 AC and dc lead-off detection Internal pace detection algorithm on 3 leads Support for user’s own pace Thoracic impedance measurement (internal/external path) Selectable reference lead Scalable noise vs. power control, power-down modes Low power operation from 11 mW (1 lead), 15 mW (3 leads), 21 mW (all electrodes) Lead or electrode data available Supports AAMI EC11:1991/(R)2001/(R)2007, AAMI EC38 R2007, EC13:2002/(R)2007, IEC60601-1 ed. 3.0 b:2005, IEC60601-2-25 ed. 2.0 :2011, IEC60601-2-27 ed. 2.0 b:2005, IEC60601-2-51 ed. 1.0 b: 2005 Fast overload recovery Low or high speed data output rates Serial interface SPI-/QSPI™-/DSP-compatible 56-lead LFCSP package (9 mm × 9 mm) 64-lead LQFP package (10 mm × 10 mm body size)

4-Channel, 4 MSPS, 12-Bit, Dual, Simultaneous Sampling SAR ADCs Features: 16-bit, 14-bit, or 12-bit dual simultaneous sampling SAR ADC Single-ended analog inputs 4-channel with 2:1 multiplexers Channel sequencer mode High throughput rate of up to 4 MSPS SNR (typical) 87.5 dB (AD7386), VREF = 3.3 V external 84 dB (AD7387), VREF = 3.3 V external 73.8 dB (AD7388) 93 dB with OSR = 8, VREF = 2.5 V internal (AD7386) On-chip oversampling functions INL (typical) ±1.5 LSB (AD7386) ±0.5 LSB (AD7387) ±0.2 LSB (AD7388) Resolution boost function 2.5 V internal reference at 10 ppm/°C (maximum) Alert function −40°C to +125°C temperature range 16-lead, 3 mm × 3 mm LFCSP

16-Bit, Isolated Sigma-Delta Modulator Features: 5 MHz to 20 MHz external clock input rate 16 bits, no missing codes Signal to noise ratio (SNR): 88 dB (typical) Effective number of bits (ENOB): 14.2 bits typical Typical offset drift vs. temperature: 1.6 μV/°C typical On-board digital isolator On-board reference See data sheet for additional featuresAD7403-EP supports defense and aerospace applications (AQEC standard) Download AD7403-EP data sheet Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/16625 DSCC Drawing Number

Dual 12-Bit CMOS DAC with Parallel Load Input Structure Features: Two 12-bit DACs in One Package DAC Ladder Resistance Matching: 0.5% Space Saving Skinny DIP and Suface Mount Packages 4-Quadrant Multiplication Low Gain Error (1 LSB max Over Temperature) Fast Interface Timing

CMOS Dual 8-Bit Buffered Multiplying DAC Features: On-Chip Latches for both DACs +12 V to +15 V Operation DACs matched to 1% Four Quadrant Multiplication TTL/CMOS Compatible from +12 V to +15 V Latch Free (Protection Schottkys not Required)

+2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC Features: Two 8-Bit DACs in One Package 8-Pin DIP/SOIC and microSOIC Packages +2.7 V to +5.5 V Operation Internal & External Reference Capability Three-Wire Serial Interface QSPI™, SPI™ and Microwire™ Compatible Individual DAC Power-Down Function On-Chip Output Buffer Rail-to-Rail Operation On-Chip Control Register Low Power Operation: 2.3 mA @3.3 V Full Power-Down to 1 µA max, typically 80 nA

+2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC Features: Two 8-Bit DACs in One Package 8-Pin DIP/SOIC and microSOIC Packages +2.7 V to +5.5 V Operation Internal & External Reference Capability Three-Wire Serial Interface QSPI™, SPI™ and Microwire™ Compatible Individual DAC Power-Down Function On-Chip Output Buffer Rail-to-Rail Operation On-Chip Control Register Low Power Operation: 2.3 mA @3.3 V Full Power-Down to 1 µA max, typically 80 nA

Single-Channel, 3 V Front-End Processor for General Purpose Applications Including Speech and Telephony Features: 16-Bit A/D Converters 16-Bit D/A Converters Programmable Input/Output Sample Rates 75 dB ADC SNR 70 db DAC SNR 64 ksps Maximum Sample Rate -90 db Crosstalk Programmable Input/Output Gain Low group Delay (25 µs per ADC ch, 50 µs per DAC ch) Flexible Serial Port Allows Up to 4 Codecs To Be Connected in Cascade Giving 8 I/O Channels Single 2.7 V to 3.3 V Supply Operation 50 mW Max Power Dissipation at 2.7 V 20-Lead SOIC/SSOP/TSSOP Packages

Quad 12-Bit Serial Voltage Output DAC Features: Guaranteed monotonic over temperature Excellent matching between DACs Unipolar or bipolar operation Buffered voltage outputs High speed serial digital interface Reset-to-zero scale or midscale Wide supply range, +5 V only to ±15 V Low power consumption (35 mW maximum) Available in 16-Lead PDIP, SOIC, and CERDIP packages