Precision Integrated Analog Front End, Controller, and PWM for Battery Test and Formation Systems Features: CC and CV battery test and formation modes with transparent and automatic switchover, for systems of 20 Ah or less Precise measurement of voltage and current Independent feedback control blocks Highly accurate, factory trimmed instrumentation and differential amplifiers In-amp for current sense gain: 66 V/V Difference amplifier for voltage sense gain: 0.4V/V Stable over temperature: offset voltage drift <0.6 µV/°C (maximum) Gain drift: <3 ppm/°C (maximum) Current sense CMRR: 120 dB minimum Popular SMPS control for charge/discharge High PWM linearity with internal ramp voltage 50 kHz to 300 kHz user controlled switching frequency Synchronization output or input with adjustable phase shift Programmable soft start

Five-Channel, Current Output DAC with Internal Reference and SPI Features: Per channel programmable output current ranges: 300 mA, 200 mA, 100 mA, 50 mA, 25 mA, 12.5 mA, 6.25 mA, and 3.125 mA  Flexible 2.1 V to VCC output supply voltages  Flexible single- or dual-supply operation 0.6 V maximum dropout voltage guaranteed Separate voltage supply per output channel Internal switches to optional negative supply Full 12-bit and 16-bit resolution at all ranges Guaranteed operation −40°C to 125°C (H-grade) Precision internal reference (10 ppm/°C maximum VREF temperature coefficient) or external reference Analog multiplexer monitors voltages and currents A/B toggle via SPI or dedicated pin 1.71 V to VCC digital input and output supply voltage 32-lead lead frame chip scale package (LFCSP)

2-Channel, 2.35 V to 5.25 V, 1 MSPS, 12-Bit A/D Converter Features: Fast Throughput Rate: 1 MSPS Specified for VDD of 2.35 V to 5.25 V Low Power: 4.8 mW typ at 1 MSPS with 3 V Supplies 15.5 mW typ at 1 MSPS with 5 V Supplies Wide Input Bandwidth: 71.4 dB min SNR at 100 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPI®/QSPI™/MICROWIRE™/DSP Compatible Standby Mode: 1 µA max Daisy Chain Mode 8-Lead TSOT Package 8-Lead MSOP Package

4-Channel 200 kSPS, 12-Bit A/D Converter with Sequencer in 16-Lead TSSOP Features: Fast throughput rate: 200 kSPS Specified for AVDD of 2.7 V to 5.25 V Low power 3.6 mW max at 200 kSPS with 3 V supply 7.5 mW max at 200 kSPS with 5 V supply 4 (single-ended) inputs with sequencer Wide input bandwidth 70 dB Min SNR at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI® -/QSPI™-/ MICROWIRE™-/DSP-compatible Shutdown mode: 0.5 μA max 16-lead TSSOP package Qualified for automotive applicationsAD7923-EP supports defense and aerospace applications (AQEC standard) Download AD7923-EP data sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Product change notification Qualification data available on request V62/12647 DSCC Drawing Number

+3.3 V/+5 V Multiplying 12-Bit DAC With an 8-Bit Byte Interface Features: 12-Bit Multiplying DACs Guaranteed Specifications wth +3.3 V/+5 Supply 0.5 LSBs INL and DNL Low Power: 5 µW typ Fast Settling: 600 ns to 0.01% with AD843 Fast Interface 40 ns Strobe Pulsewidth (AD7943) 40 ns Write Pulsewidth (AD7945, A7948) Low Glitch: 60 nV-s with Amplifier Connected

+3.3 V/+5 V Multiplying 12-Bit DAC With a Serial Interface Features: 12-Bit Multiplying DACs 0.5 LSBs INL and DNL Fast Interface 40 ns Strobe Pulsewidth (AD7943) 40 ns Write Pulsewidth (AD7945, A7948) Guaranteed Specifications wth +3.3 V/+5 Supply Low Power: 5 µW typ Low Glitch: 60 nV-s with Amplifier Connected Fast Settling: 600 ns to 0.01% with AD843

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC Features: SNR: 83 dB (85 dBFS) to 10 MHz input SFDR: 87 dBc to 10 MHz input Noise figure: 15 dB Input impedance: 1 kΩ Power: 600 mW 1.8 V analog supply operation 1.8 V to 3.3 V output supply Selectable bandwidth 2.5 MHz/5 MHz/10 MHz real 5 MHz/10 MHz/20 MHz complex Output data rate: 30 MSPS to 160 MSPS See data sheet for additional features

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 109 mW per channel at 12 bits/40 MSPS (TGC) 70 mW per channel in CW Doppler Flexible power-down modes Overload recovery in <10 ns See data sheet for additional features

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity