The ADAU1962A is a high performance, single-chip digital-to-analog converter (DAC) that provides 12 DACs with differential or single-ended outputs using the Analog Devices, Inc., patented multibit Σ-Δ architecture. A serial peripheral interface (SPI)/I2C port is included, allowing a microcontroller to adjust volume and many other parameters. The ADAU1962A operates from 2.5 V digital and 3.3 V analog supplies. A linear regulator is included to generate the digital supply voltage from the analog supply voltage. The ADAU1962A is available in an 80-lead LQFP.The ADAU1962A is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the internal master clock from an external left-right frame clock (LRCLK), the ADAU1962A can eliminate the need for a separate high frequency master clock andcan be used with or without a bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 2.5 V digital supplies, power consumption is minimized, and the digital waveforms are asmaller amplitude, further reducing emissions.Note that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant.APPLICATIONS Automotive audio systems Home theater systems Digital audio effects processors

The ADAU1966A is a high performance, single-chip digital-to-analog converter (DAC) that provides 16 DACs with differential or single-ended outputs using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ) architecture. A serial peripheral interface (SPI)/I2C port is included, allowing a microcontroller to adjust volume and many other parameters. The ADAU1966A operates from 2.5 V digital and 3.3 V analog supplies. A linear regulator is included to generate the digital supply voltage from the analog supply voltage. The ADAU1966A is available in an 80-lead LQFP.The ADAU1966A is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the internal master clock from an external left-right frame clock (LRCLK), the ADAU1966A can eliminate the need for a separate high frequency master clock and can be used with or without a bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 2.5 V digital supplies, power consumption is minimized, and the digital waveforms are a smaller amplitude, further reducing emissions.Note that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant.APPLICATIONS Automotive audio systems Home theater systems Digital audio effects processors

The ADAU1979 incorporates four high performance, analog-to-digital converters (ADCs) with 4.5 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI. An I2C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1979 uses only a single 3.3 V supply. The device internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system. The ADAU1979 is available in a 40-lead LFCSP package.Note that throughout the data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only that function is relevant.APPLICATIONS Automotive audio systems Active noise cancellation systems

14-Bit, 65Msps Low Power Octal ADCs Features:8-Channel Simultaneous Sampling ADC73dB SNR90dB SFDRLow Power: 88mW/59mW/46mW per ChannelSingle 1.8V SupplySerial LVDS Outputs: 1 or 2 Bits per ChannelSelectable Input Ranges: 1VP-P to 2VP-P800MHz Full Power Bandwidth S/HShutdown and Nap ModesSerial SPI Port for ConfigurationInternal Bypass Capacitance, No External Components140-Pin (11.25mm × 9mm) BGA Package

16-Bit, 50Msps DAC Features: 50Msps Update Rate Pin Compatible 12-Bit, 14-Bit and 16-Bit Devices High Spectral Purity: 87dB SFDR at 1MHz fOUT 5pV-s Glitch Impulse Differential Current Outputs 20ns Settling Time Low Power: 180mW from ±5V Supplies TTL/CMOS (3.3V or 5V) Inputs Small Package: 28-Pin SSOP

Five-Channel, Current Output DAC with Internal Reference and SPI Features: Per channel programmable output current ranges: 300 mA, 200 mA, 100 mA, 50 mA, 25 mA, 12.5 mA, 6.25 mA, and 3.125 mA  Flexible 2.1 V to VCC output supply voltages  Flexible single- or dual-supply operation 0.6 V maximum dropout voltage guaranteed Separate voltage supply per output channel Internal switches to optional negative supply Full 12-bit and 16-bit resolution at all ranges Guaranteed operation −40°C to 125°C (H-grade) Precision internal reference (10 ppm/°C maximum VREF temperature coefficient) or external reference Analog multiplexer monitors voltages and currents A/B toggle via SPI or dedicated pin 1.71 V to VCC digital input and output supply voltage 32-lead lead frame chip scale package (LFCSP)

8-Channel, 24-Bit, Simultaneous Sampling ADC Features: 8-channel, 24-bit simultaneous sampling ADC Single-ended or true differential inputs PGA per channel (gains of 1, 2, 4, and 8) Low dc input current ±4 nA (differential)/±8 nA (single-ended) Up to 128 kSPS ODR per channel Programmable ODRs and bandwidth SRC for coherent sampling Sampling rate resolution up to 15.2 × 10−6 SPS Low latency sinc3 and sinc5 filter paths Adjustable phase synchronization Internal 2.5 V reference Two power modes High resolution mode Low power mode Optimizes power dissipation and performance Low resolution SAR ADC for system and chip diagnostics Power supply Bipolar (±1.65 V) or unipolar (3.3 V) supplies Digital I/O supply: 1.8 V to 3.6 V Performance temperature range: −40°C to +105°C Functional temperature range: −40°C to +125°C Performance Combined ac and dc performance 107 dB SNR/dynamic range at 32 kSPS in high resolution mode (sinc5) −109 dB THD ±8 ppm of FSR INL ±15 μV offset error ±0.1% FS gain error ±10 ppm/°C typical temperature coefficient

18-Bit, 5 MSPS PULSAR Differential ADC Features: Throughput: 5 MSPS 18-bit resolution with no missing codes SNR 99 dB INL +/-0.8 LSB DNL +/-0.5 LSB True differential analog input voltage range: ±4.096 V or ±5 V Low power dissipation (39 mW) SAR architecture External reference options Serial LVDS interface 32-lead, 5mm × 5mm LFCSP (QFN) See datasheet for more details

18-Bit, 2 MSPS PulSAR 15 mW ADC in QFN Features: 18-bit resolution with no missing codes Throughput: 2 MSPS (TURBO = high), 1.5 MSPS (TURBO = low) Low power dissipation 15 mW at 2 MSPS, with external reference 26 mW at 2 MSPS with internal reference INL: ±1 LSB typical, ±2.5 LSB maximum SNR 95.5 dB, with on-chip reference 97.0 dB, with external reference 4.096 V internal reference: typical drift of 10 ppm/°C True differential analog input voltage range: ±VREF 0 V to VREF with VREF up to 5.0 V Allows use of any input range See data sheet for additional features

Precision Integrated Analog Front End, Controller, and PWM for Battery Test and Formation Systems Features: CC and CV battery test and formation modes with transparent and automatic switchover, for systems of 20 Ah or less Precise measurement of voltage and current Independent feedback control blocks Highly accurate, factory trimmed instrumentation and differential amplifiers In-amp for current sense gain: 66 V/V Difference amplifier for voltage sense gain: 0.4V/V Stable over temperature: offset voltage drift <0.6 µV/°C (maximum) Gain drift: <3 ppm/°C (maximum) Current sense CMRR: 120 dB minimum Popular SMPS control for charge/discharge High PWM linearity with internal ramp voltage 50 kHz to 300 kHz user controlled switching frequency Synchronization output or input with adjustable phase shift Programmable soft start