Quad, Low Power, 12-Bit, 180 MSPS, Digital-to-Analog Converter and Waveform Generator Features: Highly integrated quad DAC On-chip 4096 × 12-bit pattern memory On-chip DDS Power dissipation at 3.3 V, 4 mA output typical 315.25 mW at 180 MSPS Power-down mode: <5 mW at 3.3 V Supply voltage: 1.8 V to 3.3 V SFDR to Nyquist: 86 dBc at 10 MHz output Phase noise at 1 kHz offset, 180 MSPS, 4 mA: −140 dBc/Hz Differential full-scale current outputs: 8 mA maximum at 3.3 V Small footprint, 5 mm × 5 mm with 3.5 mm × 3.6 mm exposed paddle, 32-lead LFCSP RoHS compliant package

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

Dual 12-Bit CMOS DAC with Parallel Load Input Structure Features: Two 12-bit DACs in One Package DAC Ladder Resistance Matching: 0.5% Space Saving Skinny DIP and Suface Mount Packages 4-Quadrant Multiplication Low Gain Error (1 LSB max Over Temperature) Fast Interface Timing

12 Channel, 8-Bit TrimDACs with Power Shutdown & Mid-Scale Preset Features: Low Cost Replaces 12 Potentiometers Individually Programmable Outputs 3-Wire SPI Compatible Serial Input Power Shutdown < 55 µWatts  Including IDD & IREF Midscale Preset, AD8802 Separate VREF Range Settling, AD8804 +3 to +5 Single Supply Operation

High Speed, 16-Bit, 500ksps Sampling A/D Converter with Shutdown Features: A Complete, 500ksps 16-Bit ADC 90dB S/(N+D) and –100dB THD (Typ) Power Dissipation: 270mW (Typ) No Pipeline Delay No Missing Codes Over Temperature Nap (7mW) and Sleep (10µW) Shutdown Modes Operates with Internal 15ppm/°C Reference or External Reference True Differential Inputs Reject Common Mode Noise 5MHz Full Power Bandwidth ±2.5V Bipolar Input Range 36-Pin SSOP Package Pin Compatible with the LTC1604

20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥77% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 1.8 MSPS/1 MSPS/500 kSPS options INL: ±3.1 ppm maximum Guaranteed 20-bit, no missing codes SNR: 100.5 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −100 dB at fIN = 100 kHz SINAD: 89 dB at fIN = 900 kHz (see Figure 17 in the data sheet) Oversampled dynamic range 104 dB for OSR = 2 131 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.7 mW at 500 kSPS (VDD only) 83 μW at 10 kSPS, 15 mW at 1.8 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

4-Channel, 4 MSPS, 12-Bit, Dual, Simultaneous Sampling SAR ADCs Features: 16-bit, 14-bit, or 12-bit dual simultaneous sampling SAR ADC Single-ended analog inputs 4-channel with 2:1 multiplexers Channel sequencer mode High throughput rate of up to 4 MSPS SNR (typical) 87.5 dB (AD7386), VREF = 3.3 V external 84 dB (AD7387), VREF = 3.3 V external 73.8 dB (AD7388) 93 dB with OSR = 8, VREF = 2.5 V internal (AD7386) On-chip oversampling functions INL (typical) ±1.5 LSB (AD7386) ±0.5 LSB (AD7387) ±0.2 LSB (AD7388) Resolution boost function 2.5 V internal reference at 10 ppm/°C (maximum) Alert function −40°C to +125°C temperature range 16-lead, 3 mm × 3 mm LFCSP

10-Bit, 105Msps ADCs Features: Sample Rate: 105Msps/80Msps 61dB SNR up to 140MHz Input 75dB SFDR up to 200MHz Input 775MHz Full Power Bandwidth S/H Single 3.3V Supply Low Power Dissipation: 475mW/366mW Selectable Input Ranges: ±0.5V or ±1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) 105Msps:LTC2222 (12-Bit), LTC2232 (10-Bit) 80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit) 48-Pin 7mm × 7mm QFN Package

16-Bit, 250ksps, Pseudo-Differential Unipolar SAR ADC with 94.7dB SNR Features:250ksps Throughput Rate±0.75LSB INL (Max)Guaranteed 16-Bit No Missing CodesLow Power: 3.4mW at 250ksps, 3.4μW at 250sps94.7dB SNR (Typ) at fIN = 2kHz–120dB THD (Typ) at fIN = 2kHzGuaranteed Operation to 125°C2.5V SupplyPseudo-Differential Unipolar Input Range: 0V to VREFVREF Input Range from 2.5V to 5.1VNo Pipeline Delay, No Cycle Latency1.8V to 5V I/O VoltagesSPI-Compatible Serial I/O with Daisy-Chain ModeInternal Conversion Clock16-Lead MSOP and 4mm × 3mm DFN Packages

Broadband Modem Mixed-Signal Front End Features: Low cost, 3.3 V CMOS MxFE® for broadband modems 10-bit digital-to-analog converter (DAC) 2×/4× interpolation filter 250 MSPS DAC update rate 10-bit, 75 MSPS ADC Low noise RxPGA Dual channel muxed input 6 dB input overload attenuator −12 dB to +48 dB (without attenuator) Third-order programmable low-pass filter Flexible digital datapath interface Half-duplex and full-duplex operation Programmable delay Tx driver disable signal Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs 64-lead LFCSP