CMOS, 5s 8-Bit Sampling ADC Features: Fast Conversion Time: 5 µs On-Chip Track/Hold Low Total Unadjusted Error: 1 LSB Full Power Signal Bandwidth: 50 kHz Single +5 V Supply 100 ns Data Access Time Low Power (15 mW typ) Low Cost Standard 18-Lead DlPs or 20-Terminal Surface Mount Packages

Single Channel, 16-Bit, Current Source & Voltage Output DAC, HART Connectivity Features: 16-bit resolution and monotonicity Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA ±0.01% FSR typical total unadjusted error (TUE) ±3 ppm FSR/°C output drift Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V 10% overrange ±0.01% FSR typical TUE ±2 ppm FSR/°C output drift Flexible serial digital interface On-chip output fault detection On-chip reference: 10 ppm/°C maximum Optional regulated DVCC output Asynchronous clear function Power supply range AVDD: 10.8 V to 40 V AVSS: −26.4 V to −3 V/0 V Current loop compliance voltage: AVDD – 2.5 V Temperature range: −40°C to +105°C TSSOP and LFCSP packages

16-Bit, Serial Input, Loop-Powered, 4mA to 20mA DAC Features: 16-bit resolution and monotonicity Pin selectable NAMUR-compliant ranges 4 mA to 20 mA 3.8 mA to 21 mA 3.2 mA to 24 mA NAMUR-compliant alarm currents Downscale alarm current = 3.2 mA Upscale alarm current = 22.8 mA/24 mA Total unadjusted error (TUE): 0.05% maximum INL error: 0.0035% FSR maximum Output TC: 3 ppm/°C typical Quiescent current: 300 μA maximum Flexible SPI-compatible serial digital interface with Schmitt triggered inputs On-chip fault alerts via FAULT pin or alarm current Automatic readback of fault register on each write cycle Slew rate control function Gain and offset adjust registers On-chip reference TC: 4 ppm/°C maximum Selectable regulated voltage output Loop voltage range: 5.5 V to 52 V Temperature range: −40°C to +105°C TSSOP and LFCSP packages

2.5 V to 5.5 V, 500 A Quad Voltage Output 12-Bit DAC in 10-Lead Packages Features: 4 buffered 12-Bit DACs in 10-lead MSOP and 10-lead LFCSP A, W Version: ±16 LSB INL, B Version: ±10 LSB INL Low power operation: 500μA @ 3V, 600μA @ 5V 2.5V to 5.5V power supply Guaranteed monotonic by design over all codes Power-down to 80nA @ 3V, 200nA @ 5V Double-buffered input logic Output range: 0V to VREF Power-on reset to 0V See data sheet for additional featuresAD5324-EP supports defense and aerospace applications (AQEC standard) Download AD5324-EP Data Sheet (pdf) Military temperature range  (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12628 DSCC Drawing Number

LC2MOS Quad 8-Bit DAC with Separate Reference Inputs Features: Four 8-Bit DACs with Output Amplifiers Separate Reference Input for Each DAC µCompatible with Double-Buffered Inputs Simultaneous Update of All Four Outputs Operates with Single or Dual Supplies Extended Temperature Range Operation No User Trims Required Skinny 24-Pin DIP, SOIC and 28-Terminal Surface Mount Packages

24-Bit, 312 kSPS, 109 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface Features: High performance 24-bit Σ-Δ ADC 115 dB dynamic range at 78.125 kHz output data rate 109 dB dynamic range at 312.5 kHz output data rate 312.5 kHz maximum fully filtered output word rate Pin-selectable oversampling rates of 64×, 128×, and 256× Low power mode Flexible serial peripheral interface (SPI) Fully differential modulator input On-chip differential amplifier for signal buffering On-chip reference buffer Full band, low-pass, finite impulse response (FIR) filter Overrange alert pin Digital gain correction registers Power-down mode Synchronization of multiple devices via the SYNC pin Daisy chaining

4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA Features: Fast settling filter option 4 differential/8 pseudo differential input channels RMS noise: 11 nV @ 4.7 Hz (gain = 128) 15.5 noise-free bits @ 2.4 kHz (gain = 128) Up to 22 noise-free bits (gain = 1) Offset drift: ±5 nV/°C Gain drift: ±1 ppm/°C Specified drift over time Automatic channel sequencer Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection 4 general-purpose digital outputs Power supply AVDD: 3 V to 5.25 V DVDD: 2.7 V to 5.25 V Current: 4.65 mA Temperature range: −40°C to +105°C 28-lead TSSOP and 32-lead LFCSP packages Interface 3-wire serial SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK

Quad, 16-Bit nanoDAC+ with 2 ppm/C On-Chip Reference and SPI Interface Features: High relative accuracy (INL): ±2 LSB maximum at 16-bits Low drift 2.5 V reference:: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP or TSSOP Total unadjusted error (TUE): 0.1% of FSR maximum Offset error: 1.5 mV maximum Gain error: 0.1 % of FSR maximum See data sheet for additional featuresAD5686R-EP supports defense and aerospace applications (AQEC standard) Download AD5686R-EP Data Sheet (pdf) Temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Enhanced product change notification Qualification data available on request V62/14335 DSCC Drawing Number

Quad, 16-Bit nanoDAC+ with 2 ppm/C On-Chip Reference and SPI Interface Features: High relative accuracy (INL): ±2 LSB maximum at 16-bits Low drift 2.5 V reference:: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP or TSSOP Total unadjusted error (TUE): 0.1% of FSR maximum Offset error: 1.5 mV maximum Gain error: 0.1 % of FSR maximum See data sheet for additional featuresAD5686R-EP supports defense and aerospace applications (AQEC standard) Download AD5686R-EP Data Sheet (pdf) Temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Enhanced product change notification Qualification data available on request V62/14335 DSCC Drawing Number

Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC Features: Complete quad, 16-bit digital-to-analog converter (DAC) Programmable output range ±10 V, ±10.2564 V, or ±10.5263 V ±1 LSB maximum INL error, ±1 LSB maximum DNL error Low noise: 60 nV/√Hz Settling time: 10 μs maximum Integrated reference buffers Output control during power-up/brownout Programmable short-circuit protection See Data Sheet for Additional InformationSupports Defense and Aerospace Applications (AQEC Standard) Download AD5764-EP Data Sheet (pdf) Extended temperature range: −55°C to +105°C Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/14622-01XE DSCC Drawing Number