12-Bit, 105Msps Low Power Dual ADCs Features: 2-Channel Simultaneous Sampling ADC 70.6dB SNR 88dB SFDR Low Power: 292mW/238mW/200mW Total, 146mW/119mW/100mW per Channel Single 1.8V Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package

12-Bit, 25Msps Low Power Dual ADCs Features: 2-Channel Simultaneous Sampling ADC 71dB SNR 90dB SFDR Low Power: 167mW/112mW/94mW Total 83mW/56mW/47mW per Channel Single 1.8V Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package

Octal 12-/10-/8-Bit I2C VOUT DACs with 10ppm/C Reference Features: Integrated Precision Reference: 2.5V Full-Scale 10ppm/°C (LTC2637-L) 4.096V Full-Scale 10ppm/°C (LTC2637-H) Maximum INL Error: 2.5LSB (LTC2637-12) Low Noise: 0.75mVP-P 0.1Hz to 200KHz Guaranteed Monotonic Over –40°C to 125°C Temperature Range Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2637-L) Ultralow Crosstalk Between DACs (<3nV•s) Low Power: 100μA per DAC at 3V (LTC2637-L) Power-On-Reset to Zero-Scale/Mid-Scale Double-Buffered Data Latches Tiny 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages

16-Bit, 125Msps Low Power Dual ADCs Features: Two-Channel Simultaneously Sampling ADC 76.8dB SNR 90dB SFDR Low Power: 370mW/308mW/200mW Total 185mW/154mW/100mW per Channel Single 1.8V Supply CMOS, DDR CMOS, or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 550MHz Full Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration 64-Pin (9mm × 9mm) QFN Package

Dual, 16-Bit, 1200 MSPS, TxDAC+Digital-to-Analog Converter Features: Flexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Digital gain and phase adjustment for sideband suppression Multiple chip synchronization interfaces See data sheet for additional featuresAD9122-EP supports defense and aerospace applications (AQEC standard) Download AD9122-EP data sheet (pdf) Military temperature range (such as −55°C to +105°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12654 DSCC Drawing Number

Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Features: Supports input data rates up to 1 GSPS Proprietary, low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at 180 MHz IF SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Input signal power detection High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Digital quadrature modulation using a numerically controlled oscillator (NCO) Nyquist band selection—mix mode Selectable 1×, 2×, 4×, and 8× interpolation filters Low power: 2.11 W at 1.6 GSPS, full operating conditions 88-lead, exposed pad LFCSP

10-Bit, 65/80/105 MSPS 3 V A/D Converter Features: Single 3 V supply operation (2.7 V to 3.3 V) SNR = 58 dBc (to Nyquist) SFDR = 77 dBc (to Nyquist) Low Power ADC Core: 96 mW at 65 MSPS 104 mW at 80 MSPS 120 mW at 105 MSPS Differential input with 300 MHz bandwidth On-chip reference and sample-and-hold amplifier DNL = ±0.25 LSB Flexible Analog Input: 1 Vp-p to 2 Vp-p Range Offset binary or twos complement data format Clock Duty Cycle Stabilizer

Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter Features: 1.8 V supply operation Low power: 110 mW per channel at 125 MSPS with scalable power options SNR = 74 dB (to Nyquist) SFDR = 90 dBc (to Nyquist) DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical) See datasheet for additional features

Octal LNA/VGA/AAF/ADC and Crosspoint Switch Features: 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) - See data sheet for additional information Variable gain amplifier (VGA) - See data sheet for additional information Antialiasing filter (AAF) - See data sheet for additional information Analog-to-digital converter (ADC) - See data sheet for additional information Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 109 mW per channel at 12 bits/40 MSPS (TGC) 70 mW per channel in CW Doppler Flexible power-down modes Overload recovery in <10 ns See data sheet for additional features

12 Channel, 8-Bit TrimDACs with Power Shutdown & Separate VREFL Input Features: Low Cost Replaces 12 Potentiometers Individually Programmable Outputs Power Shutdown < 55 µWatts Including IDD & IREF 3-Wire SPI Compatible Serial Input Midscale Preset, AD8802 Separate VREF Range Settling, AD8804 +3 to +5 Single Supply Operation