Dual, 12-Bit, 80 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter Features: 1.8 V supply operation Low power: 115 mW per channel at 125 MSPS with scalable power options SNR = 71 dBFS (to Nyquist) SFDR = 93 dBc at 70 MHz DNL = −0.1 LSB to +0.2 LSB (typical); INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) and low power, reduced range option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input voltage range Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Clock divider Programmable output clock and data alignment Programmable output resolution Standby mode

Quad 14-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface Features: High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range

Quad 16-/14-/12-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface

Quad, Current-Output, Serial-Input 16-/14-Bit DACs Features: 16-bit resolution INL of ±1 LSB (B Grade) 2 mA full-scale current ± 20%, with VREF = ±10 V 0.9 μs settling time to ±0.1% 12 MHz multiplying bandwidth Midscale glitch of −1 nV-sec Midscale or zero-scale reset Four separate, 4-quadrant multiplying reference inputs Compact 28-lead SSOP and 32-lead LFCSP See data sheet for additional featuresAD5544-EP supports defense and aerospace applications (AQEC standard) Download AD5544-EP Data Sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12663 DSCC Drawing Number

Low Voltage Controller for Touch Screens Features: 4-wire touch screen interface 1.6 V to 3.6 V operation Median and averaging filter to reduce noise Automatic conversion sequencer and timer User-programmable conversion parameters Auxiliary analog input/battery monitor (0.5 V to 5 V) 1 optional GPIO Interrupt outputs (INT, PENIRQ) Touch-pressure measurement Wake-up on touch function Shutdown mode: 6 μA maximum 12-ball, 1.6 mm × 2 mm WLCSP 16-lead, 4 mm × 4 mm LFCSP

1.6 V, Micropower 12-/10-/8-Bit ADCs

2.5 V to 5.5 V, 230 A, Dual Rail-to-Rail Voltage Output 12-Bit DAC Features: AD5313: 2 buffered 10-bit DACs in 1 package A version: ±4 LSB INL B version: ±2 LSB INL AD5323: 2 buffered 12-bit DACs in 1 package A version: ±16 LSB INL  B version: ±8 LSB INL 16-lead TSSOP package Power-down to 200 nA @ 5 V, 50 nA @ 3 V Micropower operation: 300 μA at 5 V (including reference current) 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 VREF Power-on-reset to 0 V

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification) Crosspoint multiplexed analog inputs 8 differential/15 pseudo differential inputs See data sheet for additional features

12-Bit, 170Msps ADCs Features: Sample Rate: 170Msps/135Msps 67.5dB SNR up to 140MHz Input 80dB SFDR up to 170MHz Input 775MHz Full Power Bandwidth S/H Single 3.3V Supply Low Power Dissipation: 890mW/660mW LVDS, CMOS, or Demultiplexed CMOS Outputs Selectable Input Ranges: ±0.5V or ±1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 185Msps: LTC2220-1 (12-Bit) 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) 64-Pin 9mm × 9mm QFN Package