The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) with sampling speeds up to 250 MSPS. The AD9613 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.The dual ADC core features a multistage, differential pipelinedarchitecture with integrated output error correction logic. EachADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC output data are routed directly to the two external 12-bit LVDS output ports and formatted either as interleaved or channel multiplexed.Flexible power-down options allow significant power savings,when desired.Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9613 is available in a 64-lead LFCSP and is specified overthe industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTS Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 400 MHz. SYNC input allows synchronization of multiple devices. 3-pin, 1.8V SPI port for register programming and register readback. Pin compatibility with the AD9643, allowing a simple migration up to 14 bits, and with the AD6649 and the AD6643.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications

The AD9628 is a monolithic, dual-channel, 1.8 V supply, 12-bit, 125 MSPS/105 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. 1.8 V CMOS or LVDS output logic levels are supported. Output data can also be multiplexed onto a single output bus.APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WIMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Hand-held scope meters Portable medical imaging Ultrasound Radar/LIDARPRODUCT HIGHLIGHTS The AD9628 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families.  The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.  A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments.  The AD9628 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9650 / AD9269 / AD9268 16-bit ADC, the AD9258 / AD9251 / AD9648 14-bit ADCs, the AD9231 12-bit ADC, and the AD9608 / AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20MSPS to 125MSPS.

The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 80 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Optical networking Test equipmentPRODUCT HIGHLIGHTS Small Footprint. Eight ADCs are contained in a small, space-saving package. Low Power of 60 mW/Channel at 80 MSPS with Scalable Power Options. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 480 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin Compatible with the AD9257 (14-Bit Octal ADC).

The AD7124-4 is a low power, low noise, completely integrated analog front end for high precision measurement applications. The device contains a low noise, 24-bit Σ-Δ analog-to-digital converter (ADC), and can be configured to have 4 differential inputs or 7 single-ended or pseudo differential inputs. The onchip low gain stage ensures that signals of small amplitude can be interfaced directly to the ADC.One of the major advantages of the AD7124-4 is that it gives the user the flexibility to employ one of three integrated power modes. The current consumption, range of output data rates, and rms noise can be tailored with the power mode selected. The device also offers a multitude of filter options, ensuring that the user has the highest degree of flexibility.The AD7124-4 can achieve simultaneous 50 Hz and 60 Hz rejection when operating at an output data rate of 25 SPS (single cycle settling), with rejection in excess of 80 dB achieved at lower output data rates.The AD7124-4 establishes the highest degree of signal chain integration. The device contains a precision, low noise, low drift internal band gap reference, and also accepts an external differential reference, which can be internally buffered. Other key integrated features include programmable low drift excitation current sources, burnout currents, and a bias voltage generator, which sets the common-mode voltage of a channel to AVDD/2. The low-side power switch enables the user to power down bridge sensors between conversions, ensuring the absolute minimal power consumption of the system. The device also allows the user the option of operating with either an internal clock or an external clock.The integrated channel sequencer allows several channels to be enabled simultaneously, and the AD7124-4 sequentially converts on each enabled channel, simplifying communication with the device. As many as 16 channels can be enabled at any time; a channel being defined as an analog input or a diagnostic such as a power supply check or a reference check. This unique feature allows diagnostics to be interleaved with conversions.The AD7124-4 also supports per channel configuration. The device allows eight configurations or setups. Each configuration consists of gain, filter type, output data rate, buffering, and reference source. The user can assign any of these setups on a channel by channel basis.The AD7124-4 also has extensive diagnostic functionality integrated as part of its comprehensive feature set. These diagnostics include a cyclic redundancy check (CRC), signal chain checks, and serial interface checks, which lead to a morerobust solution. These diagnostics reduce the need for external components to implement diagnostics, resulting in reduced board space needs, reduced design cycle times, and cost savings. The failure modes effects and diagnostic analysis (FMEDA) of a typical application has shown a safe failure fraction (SFF) greater than 90% according to IEC 61508.The device operates with a single analog power supply from 2.7 V to 3.6 V or a dual 1.8 V power supply. The digital supply has a range of 1.65 V to 3.6 V. It is specified for a temperature range of −40°C to +105°C. The AD7124-4 is housed in a 32-lead LFCSP package or a 24-lead TSSOP package.Applications Temperature measurement  Pressure measurement  Industrial process control  Instrumentation Smart transmitters Smart transmitters

The AD7124-8 is a low power, low noise, completely integratedanalog front end for high precision measurement applications.The device contains a low noise, 24-bit Σ-Δ analog-to-digitalconverter (ADC), and can be configured to have 8 differentialinputs or 15 single-ended or pseudo differential inputs. The onchiplow gain stage ensures that signals of small amplitude canbe interfaced directly to the ADC.One of the major advantages of the AD7124-8 is that it gives theuser the flexibility to employ one of three integrated powermodes. The current consumption, range of output data rates,and rms noise can be tailored with the power mode selected.The device also offers a multitude of filter options, ensuring thatthe user has the highest degree of flexibility.The AD7124-8 can achieve simultaneous 50 Hz and 60 Hzrejection when operating at an output data rate of 25 SPS (singlecycle settling), with rejection in excess of 80 dB achieved at loweroutput data rates.The AD7124-8 establishes the highest degree of signal chainintegration. The device contains a precision, low noise, lowdrift internal band gap reference and accepts an externaldifferential reference, which can be internally buffered. Otherkey integrated features include programmable low drift excitationcurrent sources, burnout currents, and a bias voltage generator,which sets the common-mode voltage of a channel to AVDD/2.The low-side power switch enables the user to power downbridge sensors between conversions, ensuring the absoluteminimal power consumption of the system. The device alsoallows the user the option of operating with either an internalclock or an external clock.The integrated channel sequencer allows several channels to beenabled simultaneously, and the AD7124-8 sequentially convertson each enabled channel, simplifying communication with thedevice. As many as 16 channels can be enabled at any time, achannel being defined as an analog input or a diagnostic suchas a power supply check or a reference check. This uniquefeature allows diagnostics to be interleaved with conversions.The AD7124-8 also supports per channel configuration. Thedevice allows eight configurations or setups. Each configurationconsists of gain, filter type, output data rate, buffering, andreference source. The user can assign any of these setups on achannel by channel basis.The AD7124-8 also has extensive diagnostic functionalityintegrated as part of its comprehensive feature set. Thesediagnostics include a cyclic redundancy check (CRC), signalchain checks, and serial interface checks, which lead to a morerobust solution. These diagnostics reduce the need for externalcomponents to implement diagnostics, resulting in reducedboard space needs, reduced design cycle times, and cost savings.The failure modes effects and diagnostic analysis (FMEDA) of atypical application has shown a safe failure fraction (SFF) greaterthan 90% according to IEC 61508.The device operates with a single analog power supply from 2.7 Vto 3.6 V or a dual 1.8 V power supply. The digital supply has arange of 1.65 V to 3.6 V. It is specified for a temperature rangeof −40°C to +125°C. The AD7124-8 is housed in a 32-leadLFCSP package.Note that, throughout this data sheet, multifunction pins, suchas DOUT/RDY, are referred to either by the entire pin name orby a single function of the pin, for example, RDY, when onlythat function is relevant.Applications Temperature measurement Pressure measurement Industrial process control Instrumentation Smart transmitters

The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter(ADC) for low bandwidth inputs. It has a maximum channelscan rate of 50 kSPS (20 µs) for fully settled data. The outputdata rates range from 5 SPS to 250 kSPS.The AD7175-2 integrates key analog and digital signal conditioningblocks to allow users to configure an individual setup foreach analog input channel in use. Each feature can be user selectedon a per channel basis. Integrated true rail-to-rail buffers on theanalog inputs and external reference inputs provide easy to drivehigh impedance inputs. The precision 2.5 V low drift (2 ppm/°C)band gap internal reference (with output reference buffer) addsembedded functionality to reduce external component count.The digital filter allows simultaneous 50 Hz/60 Hz rejection at27.27 SPS output data rate. The user can switch betweendifferent filter options according to the demands of eachchannel in the application. The ADC automatically switchesthrough each selected channel. Further digital processingfunctions include offset and gain calibration registers,configurable on a per channel basis.The device operates with a 5 V AVDD1, or ±2.5 V AVDD1/AVSS,and 2 V to 5 V AVDD2 and IOVDD supplies. The specifiedoperating temperature range is −40°C to +105°C. The AD7175-2 isin a 24-lead TSSOP package.Applications Process control: PLC/DCS modules Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography

The AD91631 is a high performance, 16-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes this DAC ideally suited for the most demanding high speed radio frequency (RF) DAC applications.Superior RF performance and deep interpolation rates enable use of the AD9163 in many wireless infrastructure applications, including MC-GSM, W-CDMA, LTE, and LTE-A.The wide bandwidth of up to 1 GHz and the complex NCO and digital upconverter enable dual band and triple band direct RF synthesis of wireless infrastructure signals, eliminating costly analog upconverters.Wide analog bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of one carrier up to 1 GHz of signal bandwidth, making it ideal for cable multiple dwelling unit (MDU) applications. A 2× interpolator filter (FIR85) enables the AD9163 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode™ operation, the AD9163 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9163 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.A serial peripheral interface (SPI) configures the AD9163 and monitors the status of all the registers. The AD9163 is offered in a 169-ball, 11 mm × 11 mm, 0.8 mm pitch CSP_BGA package.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. Up to eight lanes JESD204B SERDES interface, flexible in terms of number of lanes and lane speed. Bandwidth and dynamic range to meet multiband wireless communications standards with margin.Applications Broadband communications systems DOCSIS 3.1 cable modem termination system (CMTS)/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure MC-GSM, W-CDMA, LTE, LTE-A, point to point

The AD91641 is a high performance, 16-bit digital-to-analog converter (DAC) and direct digital synthesizer (DDS) that supports update rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.The DDS consists of a bank of 32, 32-bit numerically controlled oscillators (NCOs), each with its own phase accumulator.When combined with a 100 MHz serial peripheral interface (SPI) and fast hop modes, phase coherent fast frequency hopping (FFH) is enabled, with several modes to support multiple applications.In baseband mode, wide analog bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of one carrier up to the full maximum spectrum of 1.791 GHz of signal bandwidth. A 2× interpolator filter (FIR85) enables the AD9164 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode™ operation, the AD9164 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9164 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.An SPI interface configures the AD9164 and monitors the status of all registers. The AD9164 is offered in a 165-ball, 8 mm × 8 mm, 0.5 mm pitch CSP_BGA package, and a 169-ball, 11 mm × 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance and multiband wireless communications standards with margin. Applications Broadband communications systems DOCSIS 3.1 CMTS/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure W-CDMA, LTE, LTE-A, point to point

The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of −157.6 dBFS and large signal spurious-free dynamic range (SFDR) performance (exceeding 85 dBFS, typical) allows low level signals to be resolved in the presence of large signals.The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the inter-face to external driving circuitry while preserving the exceptional performance of the ADC.The AD9652 can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider used to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle. The 16-bit output data (with an overrange bit) from each ADC is interleaved onto a single LVDS output port along with a double data rate (DDR) clock. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9652 is available in a 144-ball CSP_BGA and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by pending U.S. patents. PRODUCT HIGHLIGHTS Integrated dual, 16-bit, 310 MSPS ADCs. On-chip buffer simplifies ADC driver interface. Operation from a 3.3 V and 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 485 MHz. SYNC input allows synchronization of multiple devices. Three-wire, 3.3 V or 1.8 V SPI port for register programming and readback. APPLICATIONS Miltary radar and communications Multimode digital receivers (3G or 4G) Test and Instrumentation Smart antenna systems

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm × 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers