The ADAS1000-3 / ADAS1000-4 measure electro cardiac (ECG)signals, thoracic impedance, pacing artifacts,and lead-on/off status and output this information in the formof a data frame supplying either lead/vector or electrode data atprogrammable data rates. Its low power and small size make itsuitable for portable, battery-powered applications. The highperformance also makes it suitable for higher end diagnosticmachines.The ADAS1000-4 is a full-featured, 3-channel ECG includingrespiration and pace detection, while the ADAS1000-3 offersonly ECG channels with no respiration or pace features.The ADAS1000-3 / ADAS1000-4 are designed to simplify thetask of acquiring and ensuring quality ECG signals. Theyprovide a low power, small data acquisition system forbiopotential applications. Auxiliary features that aid in betterquality ECG signal acquisition include: multichannel averageddriven lead, selectable reference drive, fast overload recovery,flexible respiration circuitry returning magnitude and phaseinformation, internal pace detection algorithm operating onthree leads, and the option of ac or dc lead-off detection.Several digital output options ensure flexibility whenmonitoring and analyzing signals. Value-added cardiac postprocessing is executed externally on a DSP, microprocessor, orFPGA.Because ECG systems span different applications, theADAS1000-3 / ADAS1000-4 feature a power/noise scalingarchitecture where the noise can be reducedat the expense of increasing power consumption. Signalacquisition channels may be shut down to save power. Datarates can be reduced to save power.To ease manufacturing tests and development as well as offerholistic power-up testing, the ADAS1000-3 / ADAS1000-4 offera suite of features, such as dc and ac test excitation via thecalibration DAC and CRC redundancy testing in addition toreadback of all relevant register address space.The input structure is a differential amplifier input therebyallowing users a variety of configuration options to best suittheir application.The ADAS1000-3 / ADAS1000-4 are available intwo package options: either a 56-lead LFCSP or a 64-leadLQFP package; they are specified over −40°C to +85°Ctemperature range.APPLICATIONSECG: monitor and diagnostic Bedside patient monitoring Portable telemetry Holter AED Cardiac defibrillators Ambulatory monitors Pace maker programmer Patient transport Stress testing

The ADAU1966A is a high performance, single-chip digital-to-analog converter (DAC) that provides 16 DACs with differential or single-ended outputs using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ) architecture. A serial peripheral interface (SPI)/I2C port is included, allowing a microcontroller to adjust volume and many other parameters. The ADAU1966A operates from 2.5 V digital and 3.3 V analog supplies. A linear regulator is included to generate the digital supply voltage from the analog supply voltage. The ADAU1966A is available in an 80-lead LQFP.The ADAU1966A is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the internal master clock from an external left-right frame clock (LRCLK), the ADAU1966A can eliminate the need for a separate high frequency master clock and can be used with or without a bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 2.5 V digital supplies, power consumption is minimized, and the digital waveforms are a smaller amplitude, further reducing emissions.Note that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant.APPLICATIONS Automotive audio systems Home theater systems Digital audio effects processors

The ADAU1977 incorporates four high performance analog-to-digital converters (ADCs) with direct-coupled inputs capable of 10 V rms. The ADC uses multibit sigma-delta (Σ-Δ) architecturewith continuous time front end for low EMI. The ADCs can be connected to the electret microphone (ECM) directly and provide the bias for powering the microphone. Built-in diagnostic circuitry detects faults on input lines and includes comprehensive diagnostics for faults on microphone inputs. The faults reported are short to battery, short to microphone bias, short to ground, short between positive and negative input pins, and open input terminals. In addition, each diagnostic fault is available as an IRQ flag for ease in system design. An I2C/SPI control port is also included. The ADAU1977 uses only a single 3.3 V supply. The part internally generates the microphone bias voltage. The microphone bias is programmable in a few steps from 5 V to 9 V. The low power architecture reduces the power consumption. An on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with a frame clock, the PLL eliminates the need for a separate high frequency master clock in the system. The ADAU1977 is available in a 40-lead LFCSP package.APPLICATIONS Automotive audio systems Active Noise Cancellation System

The ADAU1977 incorporates four high performance analog-to-digital converters (ADCs) with direct-coupled inputs capable of 10 V rms. The ADC uses multibit sigma-delta (Σ-Δ) architecturewith continuous time front end for low EMI. The ADCs can be connected to the electret microphone (ECM) directly and provide the bias for powering the microphone. Built-in diagnostic circuitry detects faults on input lines and includes comprehensive diagnostics for faults on microphone inputs. The faults reported are short to battery, short to microphone bias, short to ground, short between positive and negative input pins, and open input terminals. In addition, each diagnostic fault is available as an IRQ flag for ease in system design. An I2C/SPI control port is also included. The ADAU1977 uses only a single 3.3 V supply. The part internally generates the microphone bias voltage. The microphone bias is programmable in a few steps from 5 V to 9 V. The low power architecture reduces the power consumption. An on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with a frame clock, the PLL eliminates the need for a separate high frequency master clock in the system. The ADAU1977 is available in a 40-lead LFCSP package.APPLICATIONS Automotive audio systems Active Noise Cancellation System

The ADAU1978 incorporates four high performance, analog-to-digital converters (ADCs) with 2 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI. An I2C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1978 uses only a single 3.3 V supply. The part internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The ADAU1978 is available in a 40-lead LFCSP package. The on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system.Note that throughout this data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only that function is relevant. APPLICATIONS Automotive audio systems Active noise cancellation system

The AD5317R, a member of the nanoDAC® family, is a low power, quad, 10-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5317R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up tozero scale or midscale and remain at that level until a valid writetakes place. Each part contains a per-channel power-downfeature that reduces the current consumption of the device to4 µA at 3 V while in power-down mode.The AD5317R employs a versatile SPI interface that operates atclock rates up to 50 MHz and contains a VLOGIC pin intended for1.8 V/3 V/5 V logic. Product Highlights Precision DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficient Two Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOPApplications Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems

The AD5683R/AD5682R/AD5681R/AD5683, members of thenanoDAC+® family, are low power, single-channel, 16-/14-/12-bitbuffered voltage out digital-to-analog converters (DACs). Thedevices, except the AD5683, include an enabled by default internal2.5 V reference, offering 2 ppm/°C drift. The output span can beprogrammed to be 0 V to VREF or 0 V to 2 × VREF. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The devices are available in a 2.00 mm ×2.00 mm, 8-lead LFCSP or a 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. TheAD5683R/AD5682R/AD5681R/AD5683 contain a power-downmode that reduces the current consumption of the device to 2 µA(maximum) at 5 V and provides software selectable output loadswhile in power-down mode.The AD5683R/AD5682R/AD5681R/AD5683 use a versatile3-wire serial interface that operates at clock rates of up to 50 MHz.Some devices also include asynchronous RESET pin and VLOGICpin options, allowing 1.8 V compatibilityProduct Highlights High Relative Accuracy (INL). AD5683R/AD5683 (16-bit): ±2 LSB maximum. Low Drift, 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 2.00 mm × 2.00 mm, 8-lead LFCSP. 10-lead MSOP.Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources

The AD5683R/AD5682R/AD5681R/AD5683, members of thenanoDAC+® family, are low power, single-channel, 16-/14-/12-bitbuffered voltage out digital-to-analog converters (DACs). Thedevices, except the AD5683, include an enabled by default internal2.5 V reference, offering 2 ppm/°C drift. The output span can beprogrammed to be 0 V to VREF or 0 V to 2 × VREF. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The devices are available in a 2.00 mm ×2.00 mm, 8-lead LFCSP or a 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. TheAD5683R/AD5682R/AD5681R/AD5683 contain a power-downmode that reduces the current consumption of the device to 2 µA(maximum) at 5 V and provides software selectable output loadswhile in power-down mode.The AD5683R/AD5682R/AD5681R/AD5683 use a versatile3-wire serial interface that operates at clock rates of up to 50 MHz.Some devices also include asynchronous RESET pin and VLOGICpin options, allowing 1.8 V compatibilityProduct Highlights High Relative Accuracy (INL). AD5683R/AD5683 (16-bit): ±2 LSB maximum. Low Drift, 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 2.00 mm × 2.00 mm, 8-lead LFCSP. 10-lead MSOP.Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources

The AD5683R/AD5682R/AD5681R/AD5683, members of thenanoDAC+® family, are low power, single-channel, 16-/14-/12-bitbuffered voltage out digital-to-analog converters (DACs). Thedevices, except the AD5683, include an enabled by default internal2.5 V reference, offering 2 ppm/°C drift. The output span can beprogrammed to be 0 V to VREF or 0 V to 2 × VREF. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The devices are available in a 2.00 mm ×2.00 mm, 8-lead LFCSP or a 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. TheAD5683R/AD5682R/AD5681R/AD5683 contain a power-downmode that reduces the current consumption of the device to 2 µA(maximum) at 5 V and provides software selectable output loadswhile in power-down mode.The AD5683R/AD5682R/AD5681R/AD5683 use a versatile3-wire serial interface that operates at clock rates of up to 50 MHz.Some devices also include asynchronous RESET pin and VLOGICpin options, allowing 1.8 V compatibilityProduct Highlights High Relative Accuracy (INL). AD5683R/AD5683 (16-bit): ±2 LSB maximum. Low Drift, 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 2.00 mm × 2.00 mm, 8-lead LFCSP. 10-lead MSOP.Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources

The AD5684, a member of the nanoDAC+™ family, is a low power, quad, 12-bit buffered voltage output DAC. The device includes a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5684 also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5684 employs a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL): ±1 LSB maximum Excellent DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Two Package Options: 3 mm × 3 mm, 16-lead LFCSP and 16-lead TSSOPApplications Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems