The AD9266 is a monolithic, single-channel 1.8 V supply,16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digitalconverter (ADC). It features a high performance sample-and-holdcircuit and on-chip voltage reference.The product uses multistage differential pipeline architecturewith output error correction logic to provide 16-bit accuracy at80 MSPS data rates and to guarantee no missing codes over thefull operating temperature range.The ADC contains several features designed to maximizeflexibility and minimize system cost, such as programmableclock and data alignment and programmable digital test patterngeneration. The available digital test patterns include built-indeterministic and pseudorandom patterns, along with customuser-defined test patterns entered via the serial port interface (SPI).A differential clock input with a selectable internal 1-to-8 divideratio controls all internal conversion cycles. An optional duty cyclestabilizer (DCS) compensates for wide variations in the clock dutycycle while maintaining excellent overall ADC performance.The interleaved digital output data is presented in offset binary,gray code, or twos complement format. A DCO is provided toensure proper latch timing with receiving logic. Both 1.8 V and3.3 V CMOS levels are supported.The AD9266 is available in a 32-lead RoHS-compliant LFCSPand is specified over the industrial temperature range (−40°Cto +85°C).Product Highlights The AD9266 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D15_D14 to D1_D0) timing and offset adjustments, and voltage reference modes. The AD9266 is packaged in a 32-lead RoHS-compliant LFCSP that is pin compatible with the AD9609 10-bit ADC, the AD9629 12-bit ADC, and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 80 MSPS.Applications Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imaging

The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The AD9269 incorporates an optional integrated dc correction and quadrature error correction block (QEC) that corrects for dc offset, gain, and phase mismatch between the two channels. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers.The ADC also contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is pro-vided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR

The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC). It is optimized for high performance over wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range.The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. The internal power-down feature supported via the SPI and typically consumes less than 5 mW when disabled.Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range. Product HighlightsIF optimization capability used to improve SFDR.Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture.Packaged in a Pb-free, 72-lead LFCSP package.Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths.Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS. ApplicationsMulticarrier, multimode cellular receiversAntenna array positioningPower amplifier linearizationBroadband wirelessRadarInfrared imagingCommunications instrumentation

The AD9629 is a monolithic, single channel 1.8 V supply, 12-bit, 20 MSPS/40 MSPS/65MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported.The AD9629 is available in a 32-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).Applications Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imagingProduct Highlights1. The AD9629 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.3. A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D11 to D0) timing and offset adjustments, and voltage reference modes.4. The AD9629 is packaged in a 32-lead RoHS compliant LFCSP that is pin compatible with the AD9609 10-bit ADC and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.

The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital converter (ADC) with a high speed serial output interface. The AD9641 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth, differential sample-and-hold, analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases the design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data is routed directly to the JESD204A serial output port. This output is at CML voltage levels. A CMOS or LVDS synchronization input (DSYNC) is provided. The flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9641 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G and 4G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipmentPRODUCT HIGHLIGHTS An on-chip PLL allows users to provide a single ADC sampling clock. The PLL multiplies the ADC sampling clock to produce the corresponding JESD204A data rate clock. The configurable JESD204A output block coded data rate supports up to 1.6 Gbps. A proprietary differential input maintains excellent SNR performance for input frequencies up to 250 MHz. Operation is from a single 1.8 V power supply. The standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), controlling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.

The AD9644 is a dual, 14-bit, analog-to-digital converter (ADC) with a high speed serial output interface and sampling speeds of either 80 MSPS or 155 MSPS.The AD9644 is designed to support communications appli-cations where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.By default, the ADC output data is routed directly to the two external JESD204A serial output ports. These outputs are at CML voltage levels. Two modes are supported such that output coded data is either sent through one data link or two. (L = 1; F = 4 or L = 2; F = 2). Independent synchronization inputs (DSYNC) are provided for each channel.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9644 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.This product is protected by a U.S. patent.Applications Communications Diversity radio systems Multimode digital receivers (3G and 4G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipmentProduct Highlights An on-chip PLL allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding data rate clock. The configurable JESD204A output block supports up to 1.6 Gbps per channel data rate when using a dedicated data link per ADC or 3.2 Gbps data rate when using a single shared data link for both ADCs. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.

The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/ 105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers, and shared integrated voltage reference, which eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC output data can be routed directly to the two external 16-bit output ports or multiplexed on a single 16-bit bus. These outputs can be set to either 1.8 V CMOS or LVDS.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9650 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and test modes. Pin compatible with the AD9268 and other dual families, AD9269, AD9251, AD9231, and AD9204. This allows a simple migration across resolutions and bandwidth. APPLICATIONS Industrial instrumentation X-Ray, MRI, and ultrasound equipment High speed pulse acquisition Chemical and spectrum analysis Direct conversion receivers Multimode digital receivers Smart antenna systems General-purpose software radios

The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/ 105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers, and shared integrated voltage reference, which eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC output data can be routed directly to the two external 16-bit output ports or multiplexed on a single 16-bit bus. These outputs can be set to either 1.8 V CMOS or LVDS.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9650 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and test modes. Pin compatible with the AD9268 and other dual families, AD9269, AD9251, AD9231, and AD9204. This allows a simple migration across resolutions and bandwidth. APPLICATIONS Industrial instrumentation X-Ray, MRI, and ultrasound equipment High speed pulse acquisition Chemical and spectrum analysis Direct conversion receivers Multimode digital receivers Smart antenna systems General-purpose software radios

The AD9739 is a 14-bit, 2.5 GSPS high performance RF digital-to-analog converter (DAC) capable of synthesizing widebandsignals from dc up to 3.0 GHz. Its DAC core features a quad-switch architecture that provides exceptionally low distortion performance with an industry-leading direct RF synthesiscapability. This feature enables multicarrier generation up to the Nyquist frequency in baseband mode as well as second andthird Nyquist zones in mix mode. The output current can be programmed over the 8.66 mA to 31.66 mA range.The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies thedigital interface with existing FGPA/ASIC technology. On-chipcontrollers are used to manage external and internal clock domainvariations over temperature to ensure reliable data transfer from the host to the DAC core. Multichip synchronization is possible with an on-chip synchronization controller. A serial peripheral interface (SPI) is used for device configuration as well as readbackof status registers.The AD9739 is manufactured on a 0.18 μm CMOS process andoperates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ballchip scale ball grid array for reduced package parasitics.Product Highlights Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mix mode operation. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS. On-chip controllers manage external and internal clock domain skews. A multichip synchronization capability. Programmable differential current output with an 8.66 mA to 31.66 mA range.Applications Broadband communications systems  Military jammers Instrumentation, automatic test equipment  Radar, avionics

The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digital-to-analog converter (DAC). The flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards.The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 × fDAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to fDAC.The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data.The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise.Product Highlights Highly integrated and configurable QAM mappers, interpolators, and upconverters for direct synthesis of one to four DOCSIS- or DVB-C-compatible channels in a block. Low noise and intermodulation distortion (IMD) performance enable high quality synthesis of signals up to 1 GHz. Flexible data interface supports LVDS for improved SFDR or CMOS input data for less demanding applications. Interface is configurable from 4-bit nibbles to 32-bit words and can run at up to 150 MHz CMOS or 150 MHz LVDS double data rate (DDR). Manufactured on a CMOS process, the AD9789 uses a proprietary switching technique that enhances dynamic performance.Applications Broadband communications systems CMTS/DVB Cellular infrastructure Point-to-point wireless