16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

Dual 12-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO Features: Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Low power, fine complex NCO allows carrier placement anywhere in DAC bandwidth while adding <300 mW power Auxiliary DACs allow I and Q gain matching and offset control Includes programmable I and Q phase compensation Internal digital upconversion capability Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed pad TQFP package

4T4R Direct RF Receiver and Transmitter Features: Flexible, reconfigurable radio common platform design Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) RF DAC/RF ADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RF clock input option Versatile digital features Selectable interpolation and decimation filters Configurable DDCs and DUCs 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC) FDUCs and FDDCs are fully bypassable 2 independent 48-bit NCOs per DUC or DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Supports real or complex digital data (8-, 12-, or 16-bit) Auxiliary features ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins support toggling between modes TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) Supports Subclass 1 Supports multidevice synchronization 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

3-Channel Sigma-Delta ADC with SPI Features: One (ADE7903) 24-bit, Σ-Δ ADC (simultaneously sampling with three ADE7912/ADE7913 ADCs) On-chip temperature sensor 4-wire SPI serial interface Standalone 24-bit, Σ-Δ ADC Up to four ADE7903 and ADE7912/ADE7913 devices clocked from a single crystal or an external clock Synchronization of multiple ADE7903 and ADE7912/ADE7913 devices ±31.25 mV peak input range for current channel ±500 mV peak input range for voltage channels Single 3.3 V supply 20-lead, wide body SOIC package Operating temperature: −40°C to +85°C

Data Conversion IC Development Tools LTC2273CUJ 16-bit, 80Msps Serial ADC, 70MHz < Ain < 140MHz, req. DC890

CMOS 12-Bit Buffered Multiplying DAC With Onboard Data Latches Features: 12-Bit Resolution Low Gain TC: 2ppm/°C typ Fast TTL Compatible Data Latches Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount Packages Single +5 V to +15 V Supply Latch Free (Schottky Protection Diode not Required) Low Cost Ideal for Battery Operated Equipment

LC2CMOS, Quad 8-Bit Voltage Output DAC Features: Four 8-Bit DACs with Output Amplifiers Skinny 20-Lead DIP, SOIC, SSOP, and PLCC Packages Microprocessor-Compatible TTL/CMOS-Compatible No User Trims Extended Temperature Range Operation Single Supply Operation Possible

Complete 12-Bit, 100 kHz, Sampling ADC (AD7870/AD7870A) Features: Complete Monolithic 12-Bit ADC with: 2 µs Track/Hold Amplifier 8 µs A/D Converter On-Chip Reference Laser-Trimmed Clock Parallel, Byte and Serial Digital Interface 57 ns Data Access Time 72 dB SNR at 10 kHz Input Frequency (AD7870, AD7875) Low Power: –60 mW typ Variety of Input Ranges: ±3 V for AD7870 0 V to +5 V for AD7875 ±10 V for AD7876

Single-Lead, Heart Rate Monitor Front End Features: Fully integrated single-lead ECG front end Low supply current: 170 μA (typical) Common-mode rejection ratio: 80 dB (dc to 60 Hz) Two or three electrode configurations High signal gain (G = 100) with dc blocking capabilities 2-pole adjustable high-pass filter Accepts up to ±300 mV of half cell potential Fast restore feature improves filter settling Uncommitted op amp 3-pole adjustable low-pass filter with adjustable gain Leads off detection: ac or dc options Integrated right leg drive (RLD) amplifier Single-supply operation: 2.0 V to 3.5 V Integrated reference buffer generates virtual ground Rail-to-rail output Internal RFI filter 8 kV HBM ESD rating Shutdown pin 20-lead 4 mm × 4 mm LFCSP package Qualified for automotive applications