Analog to Digital Converters - ADC 16-Bit 1 MSPS SAR Unipolar ADC with Ref

Analog to Digital Converters - ADC 14Bit 80Msps Dual ADC w/serial LVDS

Analog Front End - AFE CCD Signal Processor w/ V-Dvr

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators Features: Dual simultaneous sampling 12-bit, 2-channel analog-to-digital converter (ADC) True differential analog inputs Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, ×128 Throughput rate per ADC 1 MSPS for AD7262 500 kSPS for AD7262-5 Analog input impedance: >1 GΩ Wide input bandwidth −3 dB bandwidth: 1.7 MHz at gain = 2 4 on-chip comparators SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32 Device offset calibration, system gain calibration On-chip reference: 2.5 V −40°C to +105°C operation High speed serial interface SPI/QSPI™/MICROWIRE/DSP compatible 48-lead LFCSP and LQFP

Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR A/D Converter Features: Dual 12-bit, 3-channel ADC Throughput rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Power consumption 7 mW at 1 MSPS with 3 V supplies 17 mW at 1 MSPS with 5 V supplies Pin-configurable analog inputs 12-channel single-ended inputs 6-channel fully differential inputs 6-channel pseudo differential inputs 70 dB SINAD at 50 kHz input frequency Accurate on-chip reference: 2.5 V ±0.2% maximum at 25°C, 20 ppm/°C maximum Dual conversion with read 875 ns, 16 MHz SCLK High speed serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible −40°C to +125°C operation Shutdown mode: 1 µA maximum 32-lead LFCSP and 32-lead TQFP

Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR A/D Converter Features: Dual 12-bit, 3-channel ADC Throughput rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Power consumption 7 mW at 1 MSPS with 3 V supplies 17 mW at 1 MSPS with 5 V supplies Pin-configurable analog inputs 12-channel single-ended inputs 6-channel fully differential inputs 6-channel pseudo differential inputs 70 dB SINAD at 50 kHz input frequency Accurate on-chip reference: 2.5 V ±0.2% maximum at 25°C, 20 ppm/°C maximum Dual conversion with read 875 ns, 16 MHz SCLK High speed serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible −40°C to +125°C operation Shutdown mode: 1 µA maximum 32-lead LFCSP and 32-lead TQFP

3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Serial Sampling ADC Features: Specified for VDD of 3 V to 5.5 V Read-Only Operation AD7853–200 kSPS; AD7853L–100 kSPS System and Self-Calibration with Autocalibration on Power-Up Automatic Power Down After Conversion (25 mW) Low Power: AD7853: 12 mW (VDD = 3 V) AD7853L: 4.5 mW (VDD = 3 V) Flexible Serial Interface: 8051/SPI®/QSPI™/µP Compatible 24-Lead DIP, SOIC and SSOP Packages