DC1299A-B: Demo Board for the LTC6421-20 Dual Matched 1.3GHz Differential Amplifiers/ADC Drivers

2.5 V to 5.5 V, 230 A, Dual Rail-to-Rail Voltage Output 12-Bit DAC Features: AD5313: 2 buffered 10-bit DACs in 1 package A version: ±4 LSB INL B version: ±2 LSB INL AD5323: 2 buffered 12-bit DACs in 1 package A version: ±16 LSB INL  B version: ±8 LSB INL 16-lead TSSOP package Power-down to 200 nA @ 5 V, 50 nA @ 3 V Micropower operation: 300 μA at 5 V (including reference current) 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 VREF Power-on-reset to 0 V

+2.5 V to 5.5 V, 400 A, Quad Rail-To-Rail Output 12-Bit DAC Features: Four 12-Bit DACS in 16-Lead TSSOP Low Power: 500 µA @ 5 V, 400 µA @ 3 V Power-Down to 300 nA @ 5 V, 90nA @ 3 V Guaranteed Monotonic by Design Power-On-Reset to Zero Volts Double-Buffered Input Logic Low Power, SPI™, QSPI™, MICROWIRE™ and DSP-Compatible 3-Wire Serial Interface Output Range: O-VREF or O-2VREF Simultaneous Update of DAC Outputs via LDAC pin (active low) Asynchronous Clear Facility via CLR pin (active low) SDO Daisy-Chaining Option Buffered/Unbuffered Reference Input Options for each DAC pair

16-Bit, Isolated Sigma-Delta Modulator Features: 5 MHz to 21 MHz master clock input frequency Offset drift vs. temperature: ±0.6 μV/°C maximum SNR: 86 dB typical 16 bits, no missing codes Full-scale analog input voltage range: ±320 mV ENOB: 14 bits typical IDD1: 10 mA maximum On-board digital isolator Operating temperature range: −40°C to +125°C High common-mode transient immunity: 150 kV/μs minimum, VDD2 = 3.3 V Wide-body SOICs 16-lead SOIC_W 8-lead SOIC_IC with increased creepage Safety and regulatory approvals (pending) UL recognition 5700 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice SA VOE Certificate of Conformity DIN V VDE V 0884-10 VlORM = 1270 VPEAK DIN V VDE V 0884-11 VlORM = 1060 VPEAK

16-Bit, Isolated, Sigma-Delta ADC Features: 5 MHz to 21 MHz master clock input frequency Offset drift vs. temperature: ±0.6 μV/°C maximum SNR: 86 dB typical 16 bits, no missing codes Full-scale analog input voltage range: ±320 mV ENOB: 14 bits typical IDD1: 10 mA maximum On-board digital isolator Operating temperature range −40°C to +125°C (16-lead SOIC_W) −40°C to +105°C (8-lead SOIC_IC) 20 V operation on VDD1 High CMTI: 150 kV/μs minimum, VDD2 = 3.3 V Wide-body SOICs 16-lead SOIC_W 8-lead SOIC_IC with increased creepage Safety and regulatory approvals UL recognition 5700 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (Pending) VDE Certificate of Conformity DIN V VDE V 0884-10: VIORM = 1270 VPEAK DIN V VDE V 0884-11: VIORM = 1060 VPEAK (Pending)

Dual Channel, 16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC Features: 16-bit resolution 16 MUPS single channel rate in fast mode 11 MUPS single channel rate in precision mode 78 ns small signal settling time to 0.1% accuracy 100 ns large signal settling time to 0.1% accuracy Ultrasmall glitch: <50 pV×s Ultralow latency: 5 ns THD: −105 dB at 1 kHz Highly configurable output voltage span and offset 1.2 V and 1.8 V logic level compatible Single (classic) and dual SPI modes Multiple error detectors, both analog and digital domains 2.5 V internal voltage reference, 10 ppm/°C maximum temperature coefficient Small package: 4 mm × 4 mm LFCSP

Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Features: 16-bit resolution 33 MUPS single channel rate in fast mode 22 MUPS single channel rate in precision mode 65 ns small signal settling time to 0.1% accuracy 100ns large signal settling time to 0.1% accuracy Ultra small glitch: < 50 pV×s Ultra low latency: 5 ns THD: −105 dB at 1 kHz Highly configurable output voltage span and offset 1.2 V and 1.8 V logic level compatible Single (classic), dual, and quad SPI modes Multiple error detectors, both analog and digital domains 2.5 V internal voltage reference, 10 ppm/°C maximum temperature coefficient 5 mm × 5 mm LFCSP

16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS options INL: ±0.4 LSB maximum Guaranteed 16-bit, no missing codes SNR: 96.2 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −99 dB at fIN = 100 kHz SINAD: 88.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 99.3 dB for OSR = 2 126 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 4.9 mW at 1 MSPS (VDD only) 80 μW at 10 kSPS, 16 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

Single Supply, 24-Bit, Sigma-Delta ADC with 10 V and 0 mA to 20 mA Inputs Features: Internal or external clock Tested for robustness per: IEC61000-4-2, IEC61000-4-3, IEC61000-4-4, IEC61000-4-5, IEC61000-4-6, CISPR 11 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 μs settling) 16 noise free bits at 1 kSPS per channel 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 4 differential or 8 single-ended Pin absolute maximum rating ±50 V Absolute input pin voltage up to ±20 V ≥1 MΩ impedance ±0.06% accuracy at 25°C 0 mA to 20 mA inputs, 4 single-ended Pin absolute maximum rating ±50 mA Input range from −0.5 mA to +24 mA 60 Ω impedance ±0.08% accuracy at 25°C On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total IDD = 3.9 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible