DC935A: Demo Board for the LTC2605 Octal I2C 16-Bit Rail-to-Rail DACs in 16-Lead SSOP.

The LTC2609/LTC2619/LTC2629 are quad 16-, 14- and 12- bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a 16?lead SSOP package. They have built-in high performance output buffers and are guaranteed monotonic.These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive and load regulation in single-supply, voltage- output DACs.The parts use a 2-wire, I2C compatible serial interface. The LTC2609/LTC2619/LTC2629 operate in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz).The LTC2609/LTC2619/LTC2629 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero-scale; after power-up, they stay at zero-scale until a valid write and update take place. The power-on reset circuit resets the LTC2609-1/LTC2619?1/ LTC2629-1 to mid-scale. The voltage outputs stay at midscale until a valid write and update take place.Applications Mobile Communications Process Control and Industrial Automation Automatic Test Equipment and Instrumentation

LC2MOS Quad 8-Bit DAC with Separate Reference Inputs Features: Four 8-Bit DACs with Output Amplifiers Separate Reference Input for Each DAC µCompatible with Double-Buffered Inputs Simultaneous Update of All Four Outputs Operates with Single or Dual Supplies Extended Temperature Range Operation No User Trims Required Skinny 24-Pin DIP, SOIC and 28-Terminal Surface Mount Packages

12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 71.3 dBFS at 9.7 MHz input 69.0 dBFS at 200 MHz input SFDR 95 dBc at 9.7 MHz input 83 dBc at 200 MHz input Low power 45 mW at 20 MSPS 85 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.16 LSB Serial port control options Offset binary, gray code, or twos complement data format Integer 1, 2, or 4 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 61.5 dBFS at 9.7 MHz input 61.0 dBFS at 200 MHz input SFDR 75 dBc at 9.7 MHz input 73 dBc at 200 MHz input Low power 45 mW at 20 MSPS 76 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.10 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment

Dual, 16-Bit, 1200 MSPS, TxDAC+Digital-to-Analog Converter Features: Flexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Digital gain and phase adjustment for sideband suppression Multiple chip synchronization interfaces See data sheet for additional featuresAD9122-EP supports defense and aerospace applications (AQEC standard) Download AD9122-EP data sheet (pdf) Military temperature range (such as −55°C to +105°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12654 DSCC Drawing Number

AD574AUFQMLR IC

Fully Accurate, Quad, 16-Bit, Buffered VOUT, 4.5 V to 5.5 V nanoDAC with SPI Interface Features: Low power quad 12-/14-/16-bit DAC, ±1 LSB INL Pin compatible and performance upgrade to AD5666 Individual and common voltage reference pin options Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale 3 power-down functions and per-channel power-down Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option 14-/16-lead TSSOP Internal reference buffer and internal output amplifier 

16-Bit, 0.5 LSB, 500 kSPS PulSAR Differential A/D Converter in MSOP/QFN Features: 16-bit resolution with no missing codes Throughput: 500 kSPS INL/DNL: ±0.25 LSB typ, ±0.5 LSB max (±8 ppm of FSR) Dynamic range: 96.5 dB SINAD: 96 dB at 1 kHz THD: −120 dB at 1 kHz True differential analog input range: ±VREF 0 V to VREF with VREF up to VDD on both inputs No pipeline delay Single-supply 5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Proprietary serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Daisy-chain multiple ADCs, selectable busy indicator Power dissipation: 40 nJ/conversion 40 μW at 5 V/1 kSPS 4 mW at 5 V/100 kSPS 18 mW at 5 V/500 kSPS Standby current: 1 nA 10-lead package: MSOP (MSOP-8 size) Pin-for-pin compatible with the 16-bit AD7687 and AD7688 and the 18-bit AD7690 and AD7691

2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DAC Features: Full 16-bit performance 3 V and 5 V single-supply operation Low 0.625 mW power dissipation 1 μs settling time Unbuffered voltage output capable of driving 60 kΩ loads directly SPI-/QSPI-/MICROWIRE-compatible interface standards Power-on reset clears DAC output to 0 V (unipolar mode) 5 kV HBM ESD classification Low glitch: 1.1 nV-sec