3V/5V, 1mW, 3-Channel Pseudo Differential, 16-Bit Sigma-Delta ADC Features: Three Pseudo Differential Input Channel ADCs 16 Bits No Missing Codes 0.003% Nonlinearity Programmable Gain Front End Gains from 1 to 128 Three-Wire Serial Interface SPI®, QSPI™, MICROWIRE™ and DSP Compatible Schmitt Trigger Input on SCLK See data sheet for additional features

14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP Features: 14-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR) SINAD: 85 dB @ 20 kHz THD: −100 dB @ 20 kHz Pseudo differential analog input range 0 V to VREF with VREF up to VDD No pipeline delay See Data Sheet for Additional Information

18-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common-mode voltage range High common-mode rejection Single-ended to differential conversion Pin selectable input range with overrange Input ranges with 4.096 V REFBUF: ±10 V, ±5 V, ±4.096 V, ±2.5 V, and ±1.5 V Gain/attenuation options: 0.37, 0.73, 0.87, 1.38, and 2.25 Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball CSP_BGA package 2.5× footprint reduction vs. discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL error: ±3.1 ppm typical, ±6.2 ppm maximum (Gain = 0.73, gain = 0.87, gain = 1.38, gain = 2.25) SINAD: 90.4 dB typical at 20 kHz (gain = 0.73) THD: −117 dB at 1 kHz, −110 dB at 100 kHz (gain = 0.73) Gain error: ±0.005%FS typical Gain error drift: ±0.13 ppm/°C typical On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: −40°C to +85°C

Dual Channel, Configurable, IsolatedDigital Input Features: Dual channel, configurable, isolated digital input Programmable trip threshold On-chip debounce filter On-chip data and power Isolation Application circuit monitors wide voltage range 10 V dc to 300 V dc 8 V rms to 240 V rms ac (with 10 ms + pickup) Negative dc protected Programmable wetting current Pulse up to 50 mA Constant current up to 6.3 mA Safety and regulatory approvals UL recognition 3750 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A (pending) CSA 61010-1: 300 V rms VDE certificate of conformity (pending) DIN V VDE V 0884-11 (VDE V 0884-11):2017-1 VIORM = 565 V peak EMC robust solution supports relay protection system level requirements ADC samples available for system diagnostics Internal SAR ADC with PGA Single 3.3 V Supply Integrated isoPower, isolated dc-to-dc converter Interfaces SPI DOUTx output reflects state of digital input IRQ interrupt pin Operating temperature: −40°C to +125°C 20-lead, LGA package with 6.8 mm creepage

High Performance Polyphase Energy Measurement IC Features: 7 high performance analog-to-digital converters (ADCs) 101 dB signal-to-noise ratio (SNR) 10,000:1 dynamic range Wide input range: ±1 V, 0.707 V rms full scale Differential inputs ±25 ppm/°C maximum channel temperature drift (including ADC, internal VREF, and PGA drift) enabling Class 0.2 meters with standard external components Power quality measurements Line frequency: 1 measurement per phase Zero crossing detection, zero-crossing timeout Phase angle measurements Supports current transformers (CTs) and Rogowski coil (di/dt) sensors Multiple range phase/gain compensation for CTs Digital integrator for Rogowski coils Flexible waveform buffer Able to resample waveform to ensure 64 points per line cycle for ease of external harmonic analysis Events can trigger waveform storage Simplifies data collection for IEC 61000-4-7 harmonic analysis Advanced metrology feature set Total active power, volt-amperes reactive (VAR), volt-amperes (VA), watthour, VAR-hour, and VA-hour Fundamental VAR and VAR-hour Current and voltage rms per phase (xIRMS, xVRMS) Supports active energy standards: IEC 62053-21, IEC 62053-22; EN50470-3; OIML R46, ANSI C12.20 Supports reactive energy standards: IEC 62053-23, IEC 62053-4 High speed communication port 10 MHz serial peripheral interface (SPI)

Dual, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter Features: Support input data rate >2 GSPS Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, or 8× interpolation filter Low power architecture Transmit enable function allows extra power saving and instant control of the output status High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Low power: 1.42 W at 1.6 GSPS full operating conditions 88-lead LFCSP with exposed pad

Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Features: Supports input data rates up to 1 GSPS Proprietary, low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at 180 MHz IF SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Input signal power detection High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Digital quadrature modulation using a numerically controlled oscillator (NCO) Nyquist band selection—mix mode Selectable 1×, 2×, 4×, and 8× interpolation filters Low power: 2.11 W at 1.6 GSPS, full operating conditions 88-lead, exposed pad LFCSP

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

16-/14-/11-Bit 2.5Gsps DACs Features:80dBc SFDR at 70MHz fOUT>68dBc SFDR from DC to 1000MHz fOUT40mA Nominal Full-Scale, ±1V Output Compliant10mA to 60mA Adjustable Full-Scale Current RangeSingle or Dual Port DDR LVDS and DHSTL InterfaceLow Latency (7.5 Cycles for Single Port, 11 Cycles for Dual Port)>78dBc 2-Tone IMD from DC to 1000MHz fOUT–165dBc/Hz Additive Phase Noise at 1MHz Offset for 65MHz fOUT170-Lead (9mm × 15mm) BGA Package

16-/14-/11-Bit 2.7Gsps DACs Features:80dBc SFDR at 50MHz fOUT>68dBc SFDR from DC to 1080MHz fOUT40mA Nominal Full-Scale, ±1V Output Compliant10mA to 60mA Adjustable Full-Scale Current RangeSingle or Dual Port DDR LVDS and DHSTL InterfaceLow Latency (7.5 Cycles for Single Port, 11 Cycles for Dual Port)>78dBc 2-Tone IMD from DC to 1000MHz fOUT–156dBc/Hz Additive Phase Noise at 1MHz Offset for 65MHz fOUT170-Lead (9mm × 15mm) BGA Package