12-Bit, 210 MSPS TxDAC D/A Converter Features: High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR at 5 MHz output, 125 MSPS: 70 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V Reference CMOS compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP Edge-triggered latches

16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

16-Bit, 100 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 100 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

Dual 12-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO Features: Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Low power, fine complex NCO allows carrier placement anywhere in DAC bandwidth while adding <300 mW power Auxiliary DACs allow I and Q gain matching and offset control Includes programmable I and Q phase compensation Internal digital upconversion capability Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed pad TQFP package

4T4R Direct RF Receiver and Transmitter Features: Flexible, reconfigurable radio common platform design Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) RF DAC/RF ADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RF clock input option Versatile digital features Selectable interpolation and decimation filters Configurable DDCs and DUCs 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC) FDUCs and FDDCs are fully bypassable 2 independent 48-bit NCOs per DUC or DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Supports real or complex digital data (8-, 12-, or 16-bit) Auxiliary features ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins support toggling between modes TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) Supports Subclass 1 Supports multidevice synchronization 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

Analog to Digital Converters - ADC LTC1853 - 8-Channel, 10-Bit/12-Bit, 400ksps, Low Power, Sampling ADCs

Analog to Digital Converters - ADC 12-BIT SINGLE CH.PARALLEL ADC I.C.

Data Conversion IC Development Tools LTC2348-16 Demo Board Octal, 16-Bit, 200ksps Simultaneous Sampling SAR ADC (req DC590, DC2026 or DC890)

Data Conversion IC Development Tools LTC2157-14: 14-bit, 250Msps, 1.8V Dual A

The AD5025 / AD5045 / AD5065 are low power, dual 12-/14-/16-bitbuffered voltage output nanoDAC® DACs offering relative accuracyspecifications of ±1 LSB INL with individual reference pins, andcan operate from a single 4.5 V to 5.5 V supply. The AD5025 /AD5045 / AD5065 also offer a differential accuracy specification of±1 LSB. The parts use a versatile 3-wire, low power Schmitttrigger serial interface that operates at clock rates up to 50 MHzand is compatible with standard SPI®, QSPI™, MICROWIRE™,and DSP interface standards. The reference for the AD5025 /AD5045 / AD5065 are supplied from an external pin and a reference buffer is provided on chip. The AD5025 / AD5045 / AD5065incorporate a power-on reset circuit that ensures the DAC outputpowers up zero scale or midscale and remains there until a validwrite takes place to the device. The AD5025 / AD5045 / AD5065contain a power-down feature that reduces the current consumptionof the device to typically 400 nA at 5 V and provides softwareselectable output loads while in power-down mode. The parts areput into power-down mode over the serial interface. Total unadjustederror for the parts is <2.5 mV. The parts exhibit very lowglitch on power-up. The outputs of all DACs can be updatedsimultaneously using the LDAC function, with the addedfunctionality of user-selectable DAC channels to simultaneouslyupdate. There is also an asynchronous CLR that clears all DACsto a software-selectable code—0 V, midscale, or full scale. Theparts also feature a power-down lockout pin, PDL, which can beused to prevent the DAC from entering power-down under anycircumstances over the serial interface.Product Highlights Dual channel available in a 14-lead TSSOP package with individual voltage reference pins. 12-/14-/16-bit accurate, ±1 LSB INL. Low glitch on power-up. High speed serial interface with clock speeds up to 50 MHz. Three power-down modes available to the user. Reset to known output voltage (zero scale or midscale). Power-down lockout capability. Applications Process controls Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators