Quad, Current-Output, Serial-Input 16-/14-Bit DACs Features: 16-bit resolution INL of ±1 LSB (B Grade) 2 mA full-scale current ± 20%, with VREF = ±10 V 0.9 μs settling time to ±0.1% 12 MHz multiplying bandwidth Midscale glitch of −1 nV-sec Midscale or zero-scale reset Four separate, 4-quadrant multiplying reference inputs Compact 28-lead SSOP and 32-lead LFCSP See data sheet for additional featuresAD5544-EP supports defense and aerospace applications (AQEC standard) Download AD5544-EP Data Sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12663 DSCC Drawing Number

Low Voltage Controller for Touch Screens Features: 4-wire touch screen interface 1.6 V to 3.6 V operation Median and averaging filter to reduce noise Automatic conversion sequencer and timer User-programmable conversion parameters Auxiliary analog input/battery monitor (0.5 V to 5 V) 1 optional GPIO Interrupt outputs (INT, PENIRQ) Touch-pressure measurement Wake-up on touch function Shutdown mode: 6 μA maximum 12-ball, 1.6 mm × 2 mm WLCSP 16-lead, 4 mm × 4 mm LFCSP

1.6 V, Micropower 12-/10-/8-Bit ADCs

True Accuracy, 16-Bit 12 V/15 V, Serial Input Voltage Output D/A Converter Features: Full 16-bit performance 1 LSB max INL and DNL Output voltage range up to ±14 V On-board reference buffers, eliminating the need for a negative reference Temperature ranges of −40°C to +85°C for A/B version/−40°C to +125°C for W/Y version Controlled output during power-on Settling time of 10 µs to 0.003% Clear function to 0 V Asynchronous update of outputs (LDAC pin) Power-on reset Serial data output for daisy chaining Data readback facility

Dual 14-Bit, 20/40/65 MSPS, 3 V Analog-to-Digital Converter Features: Integrated Dual 14-Bit Analog-to-Digital Converters Single 3 V Supply Operation (2.7 V to 3.6 V) SNR = 71.6 dBc (to Nyquist, AD9248-65) SFDR = 80 dBc (to Nyquist, AD9248-65) Low Power: 300 mW at 65 MSPS Differential Input with 500 MHz 3 dB Bandwidth Exceptional Cross Talk Immunity > 85 dB On-Chip Reference and SHA Flexible Analog Input: 1 Vp-p to 2 Vp-p Range Offset Binary or Twos Complement Data Format Clock Duty Cycle Stabilizer Output datamux option

Dual Low Power, 8-Bit TxDAC Digital-to-Analog Converters Features:Power dissipation @ 3.3 V, 20 mA output191 mW @ 10 MSPS 232 mW @ 125 MSPSSleep mode: Supply voltage: 1.8 V to 3.3 VSFDR to Nyquist86 dBc @ 1 MHz output 85 dBc @ 10 MHz outputNSD @ 10 MHz output, 125 MSPS, 20 mA: 132 dBc/Hz Differential current outputs: 4 mA to 20 mA2 on-chip auxiliary DACsCMOS inputs with single-port operationOutput common mode: adjustable 0 V to 1.2 VSmall footprint 40-lead LFCSP RoHS-compliant package

Dual Low Power, 10-Bit TxDAC Digital-to-Analog Converters Features:Power dissipation @ 3.3 V, 20 mA output 191 mW @ 10 MSPS 232 mW @ 125 MSPSSleep mode: Supply voltage: 1.8 V to 3.3 VSFDR to Nyquist 86 dBc @ 1 MHz output 85 dBc @ 10 MHz outputNSD @ 10 MHz output, 125 MSPS, 20 mA: 143 dBc/HzDifferential current outputs: 4 mA to 20 mA2 on-chip auxiliary DACsCMOS inputs with single-port operationOutput common mode: adjustable 0 V to 1.2 VSmall footprint 40-lead LFCSP RoHS-compliant package

Dual 12-Bit, LVDS Interface 500 MSPS DAC Features: High dynamic range, dual DAC parts LVDS inputs with dual-port or optional interleaved single-port operation Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF Innovative switching output stage permits usable outputs beyond Nyquist frequency LVDS inputs with dual-port or optional interleaved singleport operation See datasheet for additional features

Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs

Complete, Quad, 14-Bit, Serial Input, Unipolar/Bipolar Voltage Output DAC Features: Complete, quad, 12-/14-/16-bit digital-to-analog converter (DAC) Software programmable output range +5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum Operates from single/dual supplies Total unadjusted error (TUE): 0.1% FSR maximum Settling time: 10 μs maximum Integrated reference buffers See data sheet for additional features