The AD9634 is a 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9634 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data are routed directly to the external 12-bit LVDS output port.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire, SPI-compatible serial interface.The AD9634 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 350 MHz. 3-pin, 1.8V SPI port for register programming and readback. Pin compatibility with the AD9642, allowing a simple migration up to 14 bits, and with the AD6672. APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications

The AD9634 is a 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9634 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data are routed directly to the external 12-bit LVDS output port.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire, SPI-compatible serial interface.The AD9634 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 350 MHz. 3-pin, 1.8V SPI port for register programming and readback. Pin compatibility with the AD9642, allowing a simple migration up to 14 bits, and with the AD6672. APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications

The AD9642 is a 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9642 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data is routed directly to the external 14-bit LVDS output port.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9642 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applicationsPRODUCT HIGHLIGHTS Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 350 MHz. 3-pin, 1.8 V SPI port for register programming and readback. Pin compatibility with the AD9634, allowing a simple migration from 14 bits to 12 bits, and with the AD6672.

The AD9683 is a 14-bit ADC with sampling speeds of up to250 MSPS. The AD9683 supports communications applicationswhere low cost, small size, wide bandwidth, and versatility aredesired.The ADC core features a multistage, differential pipelinedarchitecture with integrated output error correction logic. TheADC core features wide bandwidth inputs supporting a varietyof user-selectable input ranges. An integrated voltage referenceeases design considerations. A duty cycle stabilizer (DCS) isprovided to compensate for variations in the ADC clock duty cycle,allowing the converter to maintain excellent performance. TheJESD204B high speed serial interface reduces board routingrequirements and lowers pin count requirements for thereceiving device.The ADC output data is routed directly to the JESD204B serialoutput lane. These outputs are at CML voltage levels. Data can besent through the lane at the maximum sampling rate of 250 MSPS,which results in a lane rate of 5 Gbps. Synchronization inputs(SYNCINB± and SYSREF±) are provided.Flexible power-down options allow significant power savings,when desired. Programmable overrange level detection issupported via the dedicated fast detect pins.Programming for setup and control is accomplished using a3-wire SPI-compatible serial interface.The AD9683 is available in a 32-lead LFCSP and is specifiedover the industrial temperature range of −40°C to +85°C.Product Highlights Integrated 14-bit, 170 MSPS/250 MSPS ADC. The configurable JESD204B output block supports lane rates up to 5 Gbps. An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. Support for an optional radio frequency (RF) clock input to ease system board design. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration.Applications Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Smart antenna systems Electronic test and measurement equipment Radar receivers COMSEC radio architectures IED detection/jamming systems General-purpose software radios Broadband data applications Ultrasound equipment

The ADAS1000-3 / ADAS1000-4 measure electro cardiac (ECG)signals, thoracic impedance, pacing artifacts,and lead-on/off status and output this information in the formof a data frame supplying either lead/vector or electrode data atprogrammable data rates. Its low power and small size make itsuitable for portable, battery-powered applications. The highperformance also makes it suitable for higher end diagnosticmachines.The ADAS1000-4 is a full-featured, 3-channel ECG includingrespiration and pace detection, while the ADAS1000-3 offersonly ECG channels with no respiration or pace features.The ADAS1000-3 / ADAS1000-4 are designed to simplify thetask of acquiring and ensuring quality ECG signals. Theyprovide a low power, small data acquisition system forbiopotential applications. Auxiliary features that aid in betterquality ECG signal acquisition include: multichannel averageddriven lead, selectable reference drive, fast overload recovery,flexible respiration circuitry returning magnitude and phaseinformation, internal pace detection algorithm operating onthree leads, and the option of ac or dc lead-off detection.Several digital output options ensure flexibility whenmonitoring and analyzing signals. Value-added cardiac postprocessing is executed externally on a DSP, microprocessor, orFPGA.Because ECG systems span different applications, theADAS1000-3 / ADAS1000-4 feature a power/noise scalingarchitecture where the noise can be reducedat the expense of increasing power consumption. Signalacquisition channels may be shut down to save power. Datarates can be reduced to save power.To ease manufacturing tests and development as well as offerholistic power-up testing, the ADAS1000-3 / ADAS1000-4 offera suite of features, such as dc and ac test excitation via thecalibration DAC and CRC redundancy testing in addition toreadback of all relevant register address space.The input structure is a differential amplifier input therebyallowing users a variety of configuration options to best suittheir application.The ADAS1000-3 / ADAS1000-4 are available intwo package options: either a 56-lead LFCSP or a 64-leadLQFP package; they are specified over −40°C to +85°Ctemperature range.APPLICATIONSECG: monitor and diagnostic Bedside patient monitoring Portable telemetry Holter AED Cardiac defibrillators Ambulatory monitors Pace maker programmer Patient transport Stress testing

The ADAU1966A is a high performance, single-chip digital-to-analog converter (DAC) that provides 16 DACs with differential or single-ended outputs using the Analog Devices, Inc., patented multibit sigma-delta (Σ-Δ) architecture. A serial peripheral interface (SPI)/I2C port is included, allowing a microcontroller to adjust volume and many other parameters. The ADAU1966A operates from 2.5 V digital and 3.3 V analog supplies. A linear regulator is included to generate the digital supply voltage from the analog supply voltage. The ADAU1966A is available in an 80-lead LQFP.The ADAU1966A is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the internal master clock from an external left-right frame clock (LRCLK), the ADAU1966A can eliminate the need for a separate high frequency master clock and can be used with or without a bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further minimize EMI. By using 2.5 V digital supplies, power consumption is minimized, and the digital waveforms are a smaller amplitude, further reducing emissions.Note that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant.APPLICATIONS Automotive audio systems Home theater systems Digital audio effects processors

The ADAU1977 incorporates four high performance analog-to-digital converters (ADCs) with direct-coupled inputs capable of 10 V rms. The ADC uses multibit sigma-delta (Σ-Δ) architecturewith continuous time front end for low EMI. The ADCs can be connected to the electret microphone (ECM) directly and provide the bias for powering the microphone. Built-in diagnostic circuitry detects faults on input lines and includes comprehensive diagnostics for faults on microphone inputs. The faults reported are short to battery, short to microphone bias, short to ground, short between positive and negative input pins, and open input terminals. In addition, each diagnostic fault is available as an IRQ flag for ease in system design. An I2C/SPI control port is also included. The ADAU1977 uses only a single 3.3 V supply. The part internally generates the microphone bias voltage. The microphone bias is programmable in a few steps from 5 V to 9 V. The low power architecture reduces the power consumption. An on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with a frame clock, the PLL eliminates the need for a separate high frequency master clock in the system. The ADAU1977 is available in a 40-lead LFCSP package.APPLICATIONS Automotive audio systems Active Noise Cancellation System

The ADAU1977 incorporates four high performance analog-to-digital converters (ADCs) with direct-coupled inputs capable of 10 V rms. The ADC uses multibit sigma-delta (Σ-Δ) architecturewith continuous time front end for low EMI. The ADCs can be connected to the electret microphone (ECM) directly and provide the bias for powering the microphone. Built-in diagnostic circuitry detects faults on input lines and includes comprehensive diagnostics for faults on microphone inputs. The faults reported are short to battery, short to microphone bias, short to ground, short between positive and negative input pins, and open input terminals. In addition, each diagnostic fault is available as an IRQ flag for ease in system design. An I2C/SPI control port is also included. The ADAU1977 uses only a single 3.3 V supply. The part internally generates the microphone bias voltage. The microphone bias is programmable in a few steps from 5 V to 9 V. The low power architecture reduces the power consumption. An on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with a frame clock, the PLL eliminates the need for a separate high frequency master clock in the system. The ADAU1977 is available in a 40-lead LFCSP package.APPLICATIONS Automotive audio systems Active Noise Cancellation System

The ADAU1978 incorporates four high performance, analog-to-digital converters (ADCs) with 2 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI. An I2C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1978 uses only a single 3.3 V supply. The part internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The ADAU1978 is available in a 40-lead LFCSP package. The on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system.Note that throughout this data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only that function is relevant. APPLICATIONS Automotive audio systems Active noise cancellation system

The LTC2345-18 is an 18-bit, low noise 8-channel simultaneous sampling successive approximation register (SAR) ADC with differential, wide common mode range inputs. Operating from a 5V low voltage supply and using the internal reference and buffer, each channel of this SoftSpanTM ADC can be independently configured on a conversion-by-conversion basis to accept ±4.096, 0V to 4.096V, ±2.048V, or 0V to 2.048V signals. Individual channels may also be disabled to increase throughput on the remaining channels.The wide input common mode range and 102dB CMRR of the LTC2345-18 analog inputs allow the ADC to directly digitize a variety of signals, simplifying signal chain design. This input signal flexibility, combined with ±5LSB INL, no missing codes at 18 bits, and 91.8dB SNR, makes the LTC2345-18 an ideal choice for many applications requiring wide dynamic range.The LTC2345-18 supports pin-selectable SPI CMOS (1.8V to 5V) and LVDS serial interfaces. Between one and eight lanes of data output may be employed in CMOS mode, allowing the user to optimize bus width and throughput.Applications Programmable Logic Controllers Industrial Process Control Medical Imaging High Speed Data Acquisition