14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs  Support for lane rates up to 16 Gbps per lane  1.65 W total power per channel at 3 GSPS (default settings)  Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO  4 cascaded half-band filters  Phase coherent NCO switching Up to 4 channels available  Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

Data Acquisition ADCs/DACs - Specialised Energy Metering IC with Pulse Output

Analog to Digital Converters - ADC 14 Bit 105 Msps high SNR 1.8V ADC

+3/+5 Volt Serial-Input Micropower 12-Bit DAC Features: Micropower - 100 µA Single Supply - 2.7 V to 5.5 V Operation Compact 1.75 mm Height SO-8 Package and 1.1 mm Height TSSOP-8 Package AD7390 - 12-Bit Resolution AD7391 - 10-Bit Resolution SPI and QSPI Serial Interface Compatible with Schmitt Trigger Inputs

IC D/A CONVERTER QUAD 8-BIT CMOS TSSOP 16PIN

IC A/D CONVERTER SINGLE 16-BIT TSSOP 10PIN

The AD5683R/AD5682R/AD5681R/AD5683, members of thenanoDAC+® family, are low power, single-channel, 16-/14-/12-bitbuffered voltage out digital-to-analog converters (DACs). Thedevices, except the AD5683, include an enabled by default internal2.5 V reference, offering 2 ppm/°C drift. The output span can beprogrammed to be 0 V to VREF or 0 V to 2 × VREF. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The devices are available in a 2.00 mm ×2.00 mm, 8-lead LFCSP or a 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. TheAD5683R/AD5682R/AD5681R/AD5683 contain a power-downmode that reduces the current consumption of the device to 2 µA(maximum) at 5 V and provides software selectable output loadswhile in power-down mode.The AD5683R/AD5682R/AD5681R/AD5683 use a versatile3-wire serial interface that operates at clock rates of up to 50 MHz.Some devices also include asynchronous RESET pin and VLOGICpin options, allowing 1.8 V compatibilityProduct Highlights High Relative Accuracy (INL). AD5683R/AD5683 (16-bit): ±2 LSB maximum. Low Drift, 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 2.00 mm × 2.00 mm, 8-lead LFCSP. 10-lead MSOP.Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources

16-Channel, 1 MSPS, 12-Bit ADC with Sequencer Features: Fast throughput rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low power at maximum throughput rates 5.4 mW maximum at 870 kSPS with 3 V supplies 12.5 mW maximum at 1 MSPS with 5 V supplies 16 (single-ended) inputs with sequencer Wide input bandwidth: 69.5 dB SNR at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface, SPI/QSPI™/MICROWIRE™/ DSP compatible Full shutdown mode: 0.5 μA maximum 28-lead TSSOP and 32-lead LFCSP packages AEC-Q100 qualified for automotive applicationsAD7490-EP supports defense and aerospace applications (AQEC standard) Download AD7490-EP Data Sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12635 DSCC Drawing Number

The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The AD9249 automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Data clock outputs (DCO?1, DCO?2) for capturing data on the output and frame clock outputs (FCO?1, FCO?2) for signaling a new output byte are provided. Individual channel power-down is supported, and the device typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation.The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9249 is available in an RoHS-compliant, 144-ball CSP-BGA. It is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Small Footprint. Sixteen ADCs are contained in a small, 10 mm ? 10 mm package. Low Power of 35 mW/Channel at 20 MSPS with scalable power options. Ease of Use. Data clock outputs (DCO?1, DCO?2) operate at frequencies of up to 455 MHz and support double data rate (DDR) operation. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.APPLICATIONS Medical imaging Communications receivers Multichannel data acquisition

The ADPD6000 is a highly integrated analog front end (AFE) designed for measuring various vital signals.The optical channel is designed as an optical transceiver, stimulating up to four light emitting diodes (LEDs) and measuring the return signal on up to four separate current inputs. The signal chain rejects signal offsets and corruption from asynchronous modulated interference, typically from ambient light, eliminating the need for optical filters or externally controlled dc cancellation circuitry.The electrocardiography (ECG) signal acquisition is designed to support low noise, diagnostic level measurement in the presence of a variety of interferers. The ECG signal chain has a number of complementary features supporting ECG measurement, such as driven reference for common-mode rejection and lead off detection to identify a fallen electrode.The body impedance analysis (BIA) signal chain is designed for body impedance measurement with a configurable excitation path and measurement path. A 12-bit digital-to-analog (DAC) is used in the excitation path to generate the sinusoid wave and high precision measurement, with configurable filters used to measure the body response of the stimulus.The data output and functional configuration use a serial port interface (SPI) on the ADPD6000. The control circuitry includes flexible LED signaling and synchronous detection, digital filters, digital wave generators, and configurable filters.The ADPD6000 is available in a 2.6 mm ? 2.6 mm, 0.4 mm pitch, 36-ball wafer level chip scale package (WLCSP).APPLICATIONS Wearable health and fitness monitors: heart rate, heart rate variability, SpO2, body impedance analysis, hydration, cuffless noninvasive blood pressure Home patient monitoring Industrial monitoring: particle and aerosol, gas, and conductivity detection