The ADM213E is one in a family of robust RS-232 and V.28 interface devices which operates from a single +5 V power supply. These products are suitable for operation in harsh electrical environments and are compliant with the EU directive on EMC (89/336/ EEC). Both the level of emissions and immunity are in compliance. EM immunity includes ESD protection in excess of ±15 kV on all I-O lines (1000-4-2), Fast Transient Burst protection (1000-4-4) and Radiated Immunity (1000-4-3). EM emissions include radiated and conducted emissions as required by Information Technology Equipment EN55022, CISPR22.All devices fully conform to the EIA-232E and CCITT V.28 specifications and operate at data rates up to 230 kbps. Shutdown and Enable control pins are provided on some of the products. The shutdown function on the ADM211E disables the charge pump and all transmitters and receivers. On the ADM213E the charge pump, all transmitters, and three of the five receivers are disabled. The remaining two receivers remain active thereby allowing monitoring of peripheral devices. This feature allows the device to be shut down until a peripheral device begins communication. The active receivers can alert the processor which can then take the ADM213E out of the shutdown mode. Operating from a single +5 V supply, four external 0.1 µF capacitors are required. The ADM206E is available in a 24-pin SO package. The ADM207E and ADM208E are available in 24-pin DIP, SO, SSOP and TSSOP packages. The ADM211E and ADM213E are available in 28-pin SO, SSOP and TSSOP packages. All products are backward compatible with earlier ADM2xx products facilitating easy upgrading of older designs.APPLICATIONS Laptop computers Notebook computers Printers Peripherals Modems

The ADM2xx family of line drivers/receivers is intended for all EIA-232-E and V.28 communications interfaces, especially in applications where ±12 V is not available. The ADM223, ADM230L, ADM235L, ADM236L and ADM241L feature a low power shutdown mode that reduces power dissipation toless than 5 µW, making them ideally suited for battery powered equipment. Two receivers remain enabled during shutdown on the ADM223. The ADM233L and ADM235L do not require any external components and are particularly useful in applications where printed circuit board space is critical.All members of the ADM230L family, except the ADM231L and the ADM239L, include two internal charge pump voltage converters that allow operation from a single +5 V supply. These converters convert the +5 V input power to the ±10 V required for RS-232 output levels. The ADM231L and ADM239L are designed to operate from +5 V and +12 V supplies.An internal +12 V to −12 V charge pump voltage converter generates the −12 V supply. The ADM2xxL is an enhanced upgrade for the AD2xx family featuring lower power consumption, faster slew rate and operation with smaller (1 µF) capacitors.

The ADM4850 / ADM4851 / ADM4852 / ADM4853 / ADM4854 /ADM4855 / ADM4856 / ADM4857 are differential line transceiverssuitable for high speed, half-duplex and full duplex data communication on multipoint bus transmission lines. Theyare designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850 / ADM4851 / ADM4852 / ADM4853 are half-duplex transceivers that sharedifferential lines and have separate enable inputs for the driver and receiver. The full duplex ADM4854 / ADM4855 / ADM4856 / ADM4857 transceivers have dedicated differential line driveroutputs and receiver inputs.The devices have a 1/8-unit load receiver input impedance, which allows up to 256 transceivers on one bus. Because only onedriver must be enabled at any time, the output of a disabled or powered down driver is three-stated to avoid overloading the bus.The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted.This guarantees that the receiver outputs are in a known state before communication begins and when communication ends.The driver outputs are slew rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses.Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit.The devices are fully specified over the commercial and industrial temperature ranges and are available in 8-lead SOIC (ADM4850through ADM4857), 8-lead LFCSP (ADM4850 / ADM4852 / ADM4853), and 8-lead MSOP (ADM4850 only) packages.Applications Low power RS-485 applications EMI sensitive systems DTE to DCE interfaces Industrial control Packet switching Local area networks Level translators

The ADM4850 / ADM4851 / ADM4852 / ADM4853 / ADM4854 /ADM4855 / ADM4856 / ADM4857 are differential line transceiverssuitable for high speed, half-duplex and full duplex data communication on multipoint bus transmission lines. Theyare designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850 / ADM4851 / ADM4852 / ADM4853 are half-duplex transceivers that sharedifferential lines and have separate enable inputs for the driver and receiver. The full duplex ADM4854 / ADM4855 / ADM4856 / ADM4857 transceivers have dedicated differential line driveroutputs and receiver inputs.The devices have a 1/8-unit load receiver input impedance, which allows up to 256 transceivers on one bus. Because only onedriver must be enabled at any time, the output of a disabled or powered down driver is three-stated to avoid overloading the bus.The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted.This guarantees that the receiver outputs are in a known state before communication begins and when communication ends.The driver outputs are slew rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses.Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit.The devices are fully specified over the commercial and industrial temperature ranges and are available in 8-lead SOIC (ADM4850through ADM4857), 8-lead LFCSP (ADM4850 / ADM4852 / ADM4853), and 8-lead MSOP (ADM4850 only) packages.Applications Low power RS-485 applications EMI sensitive systems DTE to DCE interfaces Industrial control Packet switching Local area networks Level translators

The ADM485 is a differential line transceiver suitable for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced data transmission and complies with both EIA Standards RS-485 and RS-422. The part contains a differential line driver and a differential line receiver. Both the driver and the receiver may be enabled independently. When disabled, the outputs are tristated.The ADM485 operates from a single +5 V power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. This feature forces the driver output into a high impedance state if during fault conditions a significant temperature increase is detected in the internal driver circuitry.Up to 32 transceivers may be connected simultaneously on a bus, but only one driver should be enabled at any time. It is important, therefore, that the remaining disabled drivers do not load the bus. To ensure this, the ADM485 driver features high output impedance when disabled and also when powered down. This minimizes the loading effect when the transceiver is not being utilized. The high impedance driver output is maintained over the entire common-mode voltage range form -7V to +12 V.The receiver contains a fail safe feature which results in a logic high output state if the inputs are unconnected (floating).The ADM485 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology. All inputs and outputs contain protection against EDS; all diver outputs feature high source and sink current capability. An epitaxial layer is used to guard against latch-up.The ADM485 features extremely fast switching speeds. Minimal driver propagation delays permit transmission at data rates up to 5 Mbits/s while low skew minimizes EMI interference. The part is fully specified over the commercial and industrial temperature range and is available in an 8-pin DIL/SOIC packages.

I/O EXPANDER, 8BIT, 400KHZ, LFCSP-24; Chip Configuration: 8bit; Bus Frequency: 400kHz; IC Interface Type: I2C; Supply Voltage Min: 1.65V; Supply Voltage Max: 3.6V; Interface Case Style: LFCSP; No. of Pins: 24Pins; No. of I/O's: 18I/O's; Product Range: ADP5587 Series; Automotive Qualification Standard: -; RoHS Phthalates Compliant: Yes; MSL: MSL 3 - 168 hours; SVHC: No SVHC (07-Jul-2017)

CAN TRANSCEIVER, 1MBPS, WSOIC-16; IC Interface Type: CAN; No. of TX Buffers: -; No. of RX Buffers: -; Supply Voltage Min: 3V; Supply Voltage Max: 5.5V; Interface Case Style: WSOIC; No. of Pins: 16Pins; Operating Temperature Min: -40°C; Operating Temperature Max: 125°C; Product Range: -; Automotive Qualification Standard: -; RoHS Phthalates Compliant: Yes; MSL: -; SVHC: No SVHC (07-Jul-2017)

The AD698 is a complete, monolithic Linear Variable Differential Transformer (LVDT) signal conditioning subsystem. It is used in conjunction with LVDTs to convert transducer mechanical position to a unipolar or bipolar dc voltage with a high degree of accuracy and repeatability. All circuit functions are included on the chip. With the addition of a few external passive components to set frequency and gain, the AD698 converts the raw LVDT output to a scaled dc signal. The device will operate with half-bridge LVDTs, LVDTs connected in the series opposed configuration (4-wire), and RVDTs.The AD698 contains a low distortion sine wave oscillator to drive the LVDT primary. Two synchronous demodulation channels of the AD698 are used to detect primary and secondary amplitude. The part divides the output of the secondary by the amplitude of the primary and multiplies by a scale factor. This eliminates scale factor errors due to drift in the amplitude of the primary drive, improving temperature performance and stability.The AD698 uses a unique ratiometric architecture to eliminate several of the disadvantages associated with traditional approaches to LVDT interfacing. The benefits of this new circuit are: no adjustments are necessary; temperature stability is improved; and transducer interchangeability is improved.The AD698 is available in two performance grades: Grade Temperature Range Package AD698AP –40°C to +85°C 28-Pin PLCC AD698SQ –55°C to +125°C 24-Pin Cerdip

The LTC4302-1/LTC4302-2 addressable I2C bus and SMBus compatible bus buffers allow a peripheral board to be inserted and removed from a live backplane without corruption of the bus. The LTC4302-1/LTC4302-2 maintain electrical isolation between the backplane and peripheral board until their VCC supply is valid and a master device on the backplane side addresses the LTC4302-1/LTC4302-2 and commands them to connect. The LTC4302-1/LTC4302-2’s ADDRESS pin provides 32 possible addresses set by an external resistive divider between VCC and GND. The LTC4302-1/LTC4302-2 work with supply voltages ranging from 2.7V to 5.5V. The SDA and SCL inputs and outputs do not load the bus lines when VCC is low.Rise time accelerator circuitry allows for heavier capacitive bus loading while still meeting system timing requirements. During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. Two general purpose input/output pins (GPIOs) on the LTC4302-1 can be configured as inputs, open-drain outputs or push-pull outputs. The LTC4302-2 option replaces one GPIO pin with a second supply voltage pin VCC2, providing level shifting between systems with different supply voltages. The LTC4302-1/LTC4302-2 are available in a 10-pin MSOP package.Applications Live Board Insertion 5V/3.3V Level Translator Servers Capacitance Buffer/Bus Extender Nested Addressing

The ADAU1961 is a low power, stereo audio codec that supports stereo 48 kHz record and playback at 35 mW from a 3.3 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control.The record path includes an integrated microphone bias circuit and six inputs. The inputs can be mixed and muxed before the ADC, or they can be configured to bypass the ADC. The ADAU1961 includes a stereo digital microphone input.The ADAU1961 includes five high power output drivers (two differential and three single-ended), supporting stereo head-phones, an earpiece, or other output transducer. AC-coupled or capless configurations are supported. Individual fine level controls are supported on all analog outputs. The output mixer stage allows for flexible routing of audio.The serial control bus supports the I2C and SPI protocols. The serial audio bus is programmable for I2S, left-/right-justified, and TDM modes. A programmable PLL supports flexible clock generation for all standard integer rates and fractional master clocks from 8 MHz to 27 MHzApplicationsAutomotive head unitsAutomotive amplifiersNavigation systemsRear-seat entertainment systems