LIGHTING DEVELOPMENT KITS;

500mA Camera LED Charge Pump Features: Low Noise Constant Frequency Operation High Efficiency: Up to 94% Multi-Mode Operation: 1x, 1.5x or 2x Boost Modes Automatic Mode Switching High Output Current: Up to 500mA Tiny Application Circuit (3mm × 3mm DFN Package All Components <1mm High) Automatic Soft-Start Output Disconnect Open, Shorted LED Protection No Inductors Internal 110m LED Current Sense Resistor 3mm × 3mm 10-Lead DFN Package

Demonstration circuit DC915 features the LT3466-1 high efficiency boost white LED driver and a step-up converter. There is one LED driver output for 6 or 8 WLEDs and a separate DC/DC converter that generates outputs for the LCD bias. VO1 drives 8 LEDs in series with 15mA LED current and VO2/VO3 can delivery ±15V at 10mA current. If the charge-pump circuitry which generates VO3 is removed (C4, C5 and D1), VO2 can deliver over 35mA of current. The input voltage range is 3V to 14V, but can go as low as 2.7V with slightly reduced output current.

Demonstration circuit 1137 is a 20mA Six White LED Driver and OLED driver with Integrated Schottky featuring the LT3498. The LT3498 is a dual output boost converter featuring a 2.3MHz PWM LED driver and a PFM (Pulse Frequency Modulation) OLED driver. The demo board is designed to operate from 3V to 5V, ideal for Li Ion battery powered dual display applications, such as main and sub-displays for cell phones. The demo board offers flexible LED dimming methods. Users can use DC dimming, filtered PWM dimming or direct PWM dimming. The parts functions as a “one-wire” current source from the LED string point of view. The circuit protection clamps LED driver output to 27V (typ) if an open circuit condition occurs. When CTRL2 is higher than 1.5V, the demo board OLED supply output voltage is 16V. It can deliver up to 24mA from a 3V source.

The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully programmable via a 2-wire serial port.Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package. APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV

Display Drivers & Controllers Digitally Adjustable LCD Bias Supply

The ADP8140 provides high current control of up to four LED drivers. Each driver can sink up to 500 mA. The sink current is programmed for all four drivers with one external resistor.The device features a feedback output that controls an external power supply for optimal efficiency. The ADP8140 also protects the LEDs, power supply, and itself against thermal events, short circuits, overvoltages, and LED open circuits. Multiple ADP8140 ICs are easily connected in parallel to drive additional LED strings or higher current LEDs. The ADP8140 is available in a small, thermally enhanced, lead frame chip scale package (LFCSP).Applications High brightness LED lighting Large format LED backlighting

The AD9984A is a complete 10-bit, 170 MSPS, monolithic analog interface optimized for capturing YPbPr video and RGB graphics signals. Its 170 MSPS encode rate capability and full power analog bandwidth of 300 MHz support all HDTV video modes up to 1080p, as well as graphics resolutions up to UXGA (1600 × 1200 at 60 Hz). The AD9984A includes a 170 MHz triple ADC with an internal reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 1.8 V power supply and an analog input. Three-state CMOS outputs can be powered from 1.8 V to 3.3 V. The AD9984A on-chip PLL generates a sample clock from the tri-level sync (for YPbPr video) or the horizontal sync (for RGB graphics). Sample clock output frequencies range from 10 MHz to 170 MHz. With internal coast generation, the PLL maintains its output frequency in the absence of a sync input. A 32-step sampling clock phase adjustment is provided. Output data, sync, and clock phase relationships are maintained. The auto-offset feature can be enabled to automatically restore the signal reference levels and calibrate out any offset differences between the three channels. The auto channel-to-channel gain-matching feature can be enabled to minimize any gain mismatches between the three channels. The AD9984A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or can be provided by the user through the CLAMP input pin. Fabricated in an advanced CMOS process, the AD9984A is provided in a space-saving, Pb-free, 80-lead low profile quad flat package (LQFP) or 64-lead lead frame chip scale package (LFCSP) and is specified over the 0°C to 70°C temperature range.APPLICATIONSAdvanced TVs Plasma display panels LCDTV HDTV RGB graphics processing LCD monitors and projectors Scan converters

SPECIALTY / SPECIALIZED INTERFACES;

4-Channel, LVDS, Dual-Output, Laser Diode Driver with Oscillator Features: Dual, current-controlled output current sources with 4 input channels TTL-selectable output Stable on-chip oscillators with independent frequency and amplitude control TTL- or LVDS-selectable write channel enables negative logic Independent TTL oscillator enables positive logic 170 mA minimum output current for the read channel 510 mA minimum output current for Write Channel 1 330 mA minimum output current for Write Channel 2 165 mA minimum output current for Write Channel 3 950 mA typical total output current Typical rise time/fall time of  0.8 ns Low power consumption Single 5 V power supply (±10%)