The ADRF6801 is a high dynamic range IQ demodulator with integrated PLL and VCO. The fractional-N PLL/synthesizer generates a frequency in the range of 3.0 GHz to 4.6 GHz. A divide-by-4 quadrature divider divides the output frequency of the VCO down to the required local oscillator (LO) frequency to drive the mixers in quadrature. Additionally, an output buffer can be enabled that generates an fVCO/2 signal for external use.The PLL reference input is supported from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential I and Q output paths have excellent quadrature accuracy and can handle baseband signaling or complex IF up to 120 MHz.The ADRF6801 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is specified over the −40°C to +85°C temperature range.APPLICATIONS QAM/QPSK RF/IF demodulators Cellular W-CDMA/CDMA/CDMA2000 Microwave point-to-(multi)point radios Broadband wireless and WiMAX

The LTC6431-15 is a gain-block amplifier with excellent linearity at frequencies beyond 1000MHz and with low associated output noise.The unique combination of high linearity, low noise and low power dissipation make this an ideal candidate for many signal-chain applications. The LTC6431-15 is easy to use, requiring a minimum of external components. It is internally input/output matched to 50Ω and it draws only 90mA from a single 5V supply.On-chip bias and temperature compensation maintain performance over environmental changes.The LTC6431-15 uses a high performance SiGe BiCMOS process for excellent repeatability compared with similar GaAs amplifiers. All A-grade LTC6431-15 devices are tested and guaranteed for OIP3 at 240MHz. The LTC6431-15 is housed in a 4mm x 4mm 24-lead QFN package with an exposed pad for thermal management and low inductance.Applications Single-Ended IF Amplifier ADC Driver CATV

The SC2200 belongs to the 4th-generation family of RF PA linearizers (RFPAL) that provides increased integration and functionality over the previous generations. The device is a dual-path linearizer that is a fully-adaptive, RFIN/RFOUT predistortion linearization solution optimized for a wide range of amplifiers, power levels, and communication protocols. It supports 2G to 4G standards (FDD and TDD) from 698MHz to 2700MHz as well as an expanded range of signal bandwidths from 60MHz down to 1.2MHz. The SC2200 accepts single-ended RF signals to eliminate baluns and features a mirrored pinout facilitating design of both paths. The device uses the PA output and input signals to adaptively generate an optimized correction function to minimize the PA’s distortion. Using RF-domain analog signal processing enables the SC2200 to operate over wide bandwidths and with very low power consumption. The dual linearizer is optimized for high-performance MIMO applications, including small cells, active antenna, and distributed antenna systems.SC2200 and SC1894 RF Power Amplifier Linearizers RF Power Amplifier Linearization Technology ApplicationsAmplifier: Class A/AB, DohertyAverage PA Output Power Examples: Cellular Infrastructure: 27dBm to 40dBmBTS Amplifiers, RRH, Booster Amplifiers, Repeaters, Small Cells, Microcells, Picocells, DAS, AAS and MIMO SystemsCellular InfrastructurePA Process: LDMOS, GaN, HBT, GaAs and InGaPSingle/Multicarrier, Multistandard: CDMA/EVDO, TD-SCDMA, WiMAX, WCDMA/HSDPA, LTE, and TD-LTEWide Range of PAs and Output Power

The AD6649 is a mixed-signal intermediate frequency (IF) receiverconsisting of dual 14-bit, 250 MSPS ADCs and a wideband digitaldownconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.The dual ADC core features a multistage, differential pipelinedarchitecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digitaldownconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.The AD6649 receiver digitizes a wide spectrum of IF frequencies.Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.Flexible power-down options allow significant power savings,when desired.Programming for setup and control is accomplished using a 3-pinSPI-compatible serial interface.The AD6649 is available in a 64-lead LFCSP and is specified overthe industrial temperature range of −40°C to +85°C.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE General-purpose software radios Broadband data applicationsPRODUCT HIGHLIGHTS Integrated dual, 14-bit, 250 MSPS ADC. Integrated wideband decimation filter and 32-bit complex NCO. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz. SYNC input allows synchronization of multiple devices. 3-pin, 1.8V SPI port for register programming and register readback.

The AD8284 is an integrated analog front end designed for low cost, compact size, flexibility, and ease of use. It contains a 4-channel differential multiplexer (mux), a 1-channel low noise preamplifier (LNA) with a programmable gain amplifier (PGA) and an antialiasing filter (AAF), as well as one direct-to-ADC channel, all integrated with a single, 12-bit analog-to-digital converter (ADC). The AD8284 also incorporates a saturation detection circuit for high frequency overvoltage conditions that would otherwise be filtered by the AAF.The analog channel features a gain range of 17 dB to 35 dB in 6 dB increments, and an ADC with a conversion rate of up to 60 MSPS. The combined input referred voltage noise of the entire channel is 3.5 nV/√Hz at maximum gain. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.Fabricated in an advanced CMOS process, the AD8284 is available in a 10 mm × 10 mm, RoHS compliant, 64-lead TQFP. It is specified over the automotive temperature range of −40°C to +105°C.APPLICATIONS Automotive radar   Adaptive cruise control   Collision avoidance   Blind spot detection   Self-parking   Electronic bumper

The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines a RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9361 receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.

The two independent direct conversion receivers have state-of-the-art noise figure and linearity. Each receive (RX) subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9361 also has flexible manual gain modes that can be externally controlled. Two high dynamic range analog-to-digital converters (ADCs) per channel digitize the received I and Q signals and pass them through configurable decimation filters and 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at the appropriate sample rate.

The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best in class TX error vector magnitude (EVM) of <−40 dB, allowing significant system margin for the external power amplifier (PA) selection. The on-board transmit (TX) power monitor can be used as a power detector, enabling highly accurate TX power measurements.

The fully integrated phase-locked loops (PLLs) provide low power fractional-N frequency synthesis for all receive and transmit channels. Channel isolation, demanded by frequency division duplex (FDD) systems, is integrated into the design. All VCO and loop filter components are integrated.

The core of the AD9361 can be powered directly from a 1.3 V regulator. The IC is controlled via a standard 4-wire serial port and four real-time input/output control pins. Comprehensive power-down modes are included to minimize power consumption during normal use. The AD9361 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA).

Applications:

• Point to point communication systems
• Femtocell/picocell/microcell base stations
• General-purpose radio systems

Features:

• RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
• TX band: 47 MHz to 6.0 GHz
• RX band: 70 MHz to 6.0 GHz
• Supports TDD and FDD operation
• Tunable channel bandwidth: <200 kHz to 56 MHz
• Dual receivers: 6 differential
• Superior receiver sensitivity with a noise figure of 2 dB at 800 MHz LO
• RX gain control
• Real-time monitor and control signals for manual gain
• Independent automatic gain control
• Dual transmitters: 4 differential outputs
• Highly linear broadband transmitter
  
  • TX EVM: ≤−40 dB
  • TX noise: ≤−157 dBm/Hz noise floor
  • TX monitor: ≥66 dB dynamic range with 1 dB accuracy
• Integrated fractional-N synthesizers
• 2.4 Hz maximum local oscillator (LO) step size
• Multichip synchronization
• CMOS/LVDS digital interface

The HMC392A is a GaAs MMIC Low Noise Amplifierdie which operates between 3.5 and 7.0 GHz. Theamplifier provides 17.2 dB of gain, 1.7 dB noisefigure, and 32.5 dBm IP3 from a +5V supply voltage.The HMC392A has six bonding adjustment optionswhich allow the user to select the bias point andoutput power of the device (+10 to +19.7 dBm). TheHMC392A amplifier can easily be integrated intoMulti-Chip-Modules (MCMs) due to its small (1.3 mm2)size. All data is with the chip in a 50 Ohm test fixtureconnected via 0.025mm (1 mil) diameter wire bonds ofminimal length 0.31mm (12 mils).Applications• Point-to-Point Radios• VSAT• LO Driver for HMC Mixers• Military EW, ECM, C3I• Space

The HMC470LP3(E) is a broadband 5-bit GaAs IC digital attenuator in low cost lead-less surface mount package. This single positive control line per bit digital attenuator incorporates off chip AC ground capacitors for near DC operation, making it suitable for a wide variety of RF and IF applications. Covering DC to 3 GHz, the insertion loss is less than 1.5 dB typical.The attenuator bit values are 1 (LSB), 2, 4, 8, and 16 dB for a total attenuation of 31 dB. Attenuation accuracy is excellent at ±0.3 dB typical step error with an IIP3 of +45 dBm. Five TTL/CMOS control inputs are used to select each attenuation state. A single Vdd bias of +5V is required.Applications Cellular; UMTS/3G Infrastructure  ISM, MMDS, WLAN, WiMAX  Microwave Radio & VSAT  Test Equipment and Sensors

The HMC470LP3(E) is a broadband 5-bit GaAs IC digital attenuator in low cost lead-less surface mount package. This single positive control line per bit digital attenuator incorporates off chip AC ground capacitors for near DC operation, making it suitable for a wide variety of RF and IF applications. Covering DC to 3 GHz, the insertion loss is less than 1.5 dB typical.The attenuator bit values are 1 (LSB), 2, 4, 8, and 16 dB for a total attenuation of 31 dB. Attenuation accuracy is excellent at ±0.3 dB typical step error with an IIP3 of +45 dBm. Five TTL/CMOS control inputs are used to select each attenuation state. A single Vdd bias of +5V is required.Applications Cellular; UMTS/3G Infrastructure  ISM, MMDS, WLAN, WiMAX  Microwave Radio & VSAT  Test Equipment and Sensors

The HMC578LC3B is a x2 active broadband frequency multiplier utilizing GaAs PHEMT technology in a leadless RoHS compliant SMT package. When driven by a +3 dBm signal, the multiplier provides +15 dBm typical output power from 24 to 33 GHz. The Fo and 3Fo isolations are >20 dBc and >30 dBc respectively at 28 GHz.The HMC578LC3B is ideal for use in LO multiplier chains for Pt to Pt & VSAT Radios yielding reduced parts count vs. traditional approaches. The low additive SSB Phase Noise of -129 dBc/Hz at 100 kHz offset helps maintain good system noise performance. The RoHS packaged HMC578LC3B eliminates the need for wire bonding, and allows the use of surface mount manufacturing techniques.APPLICATIONS Clock Generation Applications: SONET OC-192 & SDH STM-64 Point-to-Point & VSAT Radios Test Instrumentation Military & Space