The ADL5505 is a TruPwr™ mean-responding (true rms) powerdetector for use in high frequency receiver and transmitter signalchains from 450 MHz to 6000 MHz. Requiring only a singlesupply between 2.5 V and 3.3 V, the detector draws less than1.8 mA. The input is internally ac-coupled and has a nominalinput impedance of 500 Ω. The rms output is a linear-respondingdc voltage with a conversion gain of 1.86 V/V rms at 900 MHz.The ADL5505 is a highly accurate, easy to use means ofdetermining the rms of complex waveforms. It can be used forpower measurements of both simple and complex waveformsbut is particularly useful for measuring high crest factor (highpeak-to-rms ratio) signals, such as W-CDMA, CDMA2000,WiMAX, WLAN, and LTE waveforms.The on-chip modulation filter provides adequate averaging formost waveforms. An on-chip, 100 Ω series resistance at theoutput, combined with an external shunt capacitor, creates a low-passfilter response that reduces the residual ripple in the dc outputvoltage.The ADL5505 offers excellent temperature stability across a30 dB range and near 0 dB measurement error across temperatureover the top portion of the dynamic range. In addition to itstemperature stability, the ADL5505 offers low process variationsthat further reduce calibration complexity.The power detector operates from −40°C to +85°C and isavailable in an 4-ball, 0.8 mm × 0.8 mm wafer-level chip scalepackage. It is fabricated on a high fT silicon BiCMOS process.Applications Power measurement of W-CDMA, CDMA2000, QPSK-/QAM-based OFDM (LTE and WiMAX), and other complex modulation waveforms RF transmitter or receiver power measurement

The ADL5536 is a 20 dB linear amplifier that operates atfrequencies up to 1 GHz. The device can be used in a widevariety of cellular, CATV, military, and instrumentationequipment.The ADL5536 provides the highest dynamic range availablefrom an internally matched IF gain block. This is accomplishedby providing extremely low noise figures and very high OIP3specifications simultaneously across the entire 1 GHz frequencyrange. The ADL5536 also provides extremely flat gain and P1dBover frequency, which are stable over temperature, power supply,and from device to device.The device is internally matched to 50 Ω at the input and output,making the ADL5536 very easy to implement in a wide varietyof applications. Only input/output ac coupling capacitors, powersupply decoupling capacitors, and an external inductor arerequired for operation.The ADL5536 is fabricated on a GaAs HBT process and has anESD rating of ±2 kV (Class 2). The device is assembled in anMSL-1 rated SOT-89 package that uses an exposed paddle forexcellent thermal impedance.The ADL5536 consumes only 105 mA on a single 5 V supplyand is fully specified for operation from −40°C to +85°C.The ADL5536 is also pin-compatible with the 16 dB gainADL5535. Fully populated evaluation boards are availablefor each amplifier.

The ADRF6801 is a high dynamic range IQ demodulator with integrated PLL and VCO. The fractional-N PLL/synthesizer generates a frequency in the range of 3.0 GHz to 4.6 GHz. A divide-by-4 quadrature divider divides the output frequency of the VCO down to the required local oscillator (LO) frequency to drive the mixers in quadrature. Additionally, an output buffer can be enabled that generates an fVCO/2 signal for external use.The PLL reference input is supported from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential I and Q output paths have excellent quadrature accuracy and can handle baseband signaling or complex IF up to 120 MHz.The ADRF6801 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is specified over the −40°C to +85°C temperature range.APPLICATIONS QAM/QPSK RF/IF demodulators Cellular W-CDMA/CDMA/CDMA2000 Microwave point-to-(multi)point radios Broadband wireless and WiMAX

The SC2200 belongs to the 4th-generation family of RF PA linearizers (RFPAL) that provides increased integration and functionality over the previous generations. The device is a dual-path linearizer that is a fully-adaptive, RFIN/RFOUT predistortion linearization solution optimized for a wide range of amplifiers, power levels, and communication protocols. It supports 2G to 4G standards (FDD and TDD) from 698MHz to 2700MHz as well as an expanded range of signal bandwidths from 60MHz down to 1.2MHz. The SC2200 accepts single-ended RF signals to eliminate baluns and features a mirrored pinout facilitating design of both paths. The device uses the PA output and input signals to adaptively generate an optimized correction function to minimize the PA’s distortion. Using RF-domain analog signal processing enables the SC2200 to operate over wide bandwidths and with very low power consumption. The dual linearizer is optimized for high-performance MIMO applications, including small cells, active antenna, and distributed antenna systems.SC2200 and SC1894 RF Power Amplifier Linearizers RF Power Amplifier Linearization Technology ApplicationsAmplifier: Class A/AB, DohertyAverage PA Output Power Examples: Cellular Infrastructure: 27dBm to 40dBmBTS Amplifiers, RRH, Booster Amplifiers, Repeaters, Small Cells, Microcells, Picocells, DAS, AAS and MIMO SystemsCellular InfrastructurePA Process: LDMOS, GaN, HBT, GaAs and InGaPSingle/Multicarrier, Multistandard: CDMA/EVDO, TD-SCDMA, WiMAX, WCDMA/HSDPA, LTE, and TD-LTEWide Range of PAs and Output Power

The AD8314 is a complete low cost subsystem for the measurement and control of RF signals in the frequency range of 100 MHz to 2.7 GHz, with a typical dynamic range of 45 dB, intended for use in a wide variety of cellular handsets and other wireless devices. It provides a wider dynamic range and better accuracy than possible using discrete diode detectors. In particular, its temperature stability is excellent over the full operating range of -40°C to +85°C.The AD8314 is available in 8-lead MSOP and 8-lead LFCSP packages and consumes 4.5 mA from a 2.7 V to 5.5 V supply. When powered down, the typical sleep current is 20 µA.An evaluation board is available for this product and may be ordered using the following product number: AD8314-EVAL. Schematic and layout for this evaluation board is contained in the product datasheet.

The AD8351 is a low cost differential amplifier useful in RF andIF applications up to 2.2 GHz. The voltage gain can be set fromunity to 26 dB using a single external gain resistor. The AD8351provides a nominal 150 Ω differential output impedance. Theexcellent distortion performance and low noise characteristicsof this device allow for a wide range of applications.The AD8351 is designed to satisfy the demanding performancerequirements of communications transceiver applications. Thedevice can be used as a general-purpose gain block, an ADCdriver, and a high speed data interface driver, among otherfunctions. The AD8351 can also be used as a single-ended-to-differentialamplifier with similar distortion products as in thedifferential configuration. The exceptionally good distortionperformance makes the AD8351 an ideal solution for 12-bit and14-bit IF sampling receiver designs.Fabricated in Analog Devices, Inc., high speed XFCB process,the AD8351 has high bandwidth that provides high frequencyperformance and low distortion. The quiescent current of theAD8351 is 28 mA typically. The AD8351 amplifier comes in acompact 10-lead MSOP package or in a 16-lead LFCSP package,and operates over the temperature range of −40°C to +85°C.Applications Differential ADC drivers Single-ended-to-differential conversion IF sampling receivers RF/IF gain blocks SAW filter interfacing AvailabilityOther RF / IF amplifiers products:AD8367 - 500 MHz Single Ended, Analog Controlled VGA AD8369 - 600 MHz, 45 dB Digitally Controlled Variable Gain Amplifier AD8350 - 1.0 GHz Differential Amplifier

The ADF4001 frequency synthesizer can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator) or VCXO (Voltage Controlled Crystal Oscillator). The N min value of 1 allows flexibility in clock generation. 

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The ADF4360-3 is a fully integrated integer-N synthesizer andvoltage controlled oscillator (VCO). The ADF4360-3 is designedfor a center frequency of 1750 MHz. In addition, there is adivide-by-2 option available, whereby the user gets an RF output of between 800 MHz and 975 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. 

The AD6649 is a mixed-signal intermediate frequency (IF) receiverconsisting of dual 14-bit, 250 MSPS ADCs and a wideband digitaldownconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.The dual ADC core features a multistage, differential pipelinedarchitecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digitaldownconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.The AD6649 receiver digitizes a wide spectrum of IF frequencies.Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.Flexible power-down options allow significant power savings,when desired.Programming for setup and control is accomplished using a 3-pinSPI-compatible serial interface.The AD6649 is available in a 64-lead LFCSP and is specified overthe industrial temperature range of −40°C to +85°C.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE General-purpose software radios Broadband data applicationsPRODUCT HIGHLIGHTS Integrated dual, 14-bit, 250 MSPS ADC. Integrated wideband decimation filter and 32-bit complex NCO. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz. SYNC input allows synchronization of multiple devices. 3-pin, 1.8V SPI port for register programming and register readback.