The ADL5505 is a TruPwr™ mean-responding (true rms) powerdetector for use in high frequency receiver and transmitter signalchains from 450 MHz to 6000 MHz. Requiring only a singlesupply between 2.5 V and 3.3 V, the detector draws less than1.8 mA. The input is internally ac-coupled and has a nominalinput impedance of 500 Ω. The rms output is a linear-respondingdc voltage with a conversion gain of 1.86 V/V rms at 900 MHz.The ADL5505 is a highly accurate, easy to use means ofdetermining the rms of complex waveforms. It can be used forpower measurements of both simple and complex waveformsbut is particularly useful for measuring high crest factor (highpeak-to-rms ratio) signals, such as W-CDMA, CDMA2000,WiMAX, WLAN, and LTE waveforms.The on-chip modulation filter provides adequate averaging formost waveforms. An on-chip, 100 Ω series resistance at theoutput, combined with an external shunt capacitor, creates a low-passfilter response that reduces the residual ripple in the dc outputvoltage.The ADL5505 offers excellent temperature stability across a30 dB range and near 0 dB measurement error across temperatureover the top portion of the dynamic range. In addition to itstemperature stability, the ADL5505 offers low process variationsthat further reduce calibration complexity.The power detector operates from −40°C to +85°C and isavailable in an 4-ball, 0.8 mm × 0.8 mm wafer-level chip scalepackage. It is fabricated on a high fT silicon BiCMOS process.Applications Power measurement of W-CDMA, CDMA2000, QPSK-/QAM-based OFDM (LTE and WiMAX), and other complex modulation waveforms RF transmitter or receiver power measurement

The ADL5536 is a 20 dB linear amplifier that operates atfrequencies up to 1 GHz. The device can be used in a widevariety of cellular, CATV, military, and instrumentationequipment.The ADL5536 provides the highest dynamic range availablefrom an internally matched IF gain block. This is accomplishedby providing extremely low noise figures and very high OIP3specifications simultaneously across the entire 1 GHz frequencyrange. The ADL5536 also provides extremely flat gain and P1dBover frequency, which are stable over temperature, power supply,and from device to device.The device is internally matched to 50 Ω at the input and output,making the ADL5536 very easy to implement in a wide varietyof applications. Only input/output ac coupling capacitors, powersupply decoupling capacitors, and an external inductor arerequired for operation.The ADL5536 is fabricated on a GaAs HBT process and has anESD rating of ±2 kV (Class 2). The device is assembled in anMSL-1 rated SOT-89 package that uses an exposed paddle forexcellent thermal impedance.The ADL5536 consumes only 105 mA on a single 5 V supplyand is fully specified for operation from −40°C to +85°C.The ADL5536 is also pin-compatible with the 16 dB gainADL5535. Fully populated evaluation boards are availablefor each amplifier.

The SC2200 belongs to the 4th-generation family of RF PA linearizers (RFPAL) that provides increased integration and functionality over the previous generations. The device is a dual-path linearizer that is a fully-adaptive, RFIN/RFOUT predistortion linearization solution optimized for a wide range of amplifiers, power levels, and communication protocols. It supports 2G to 4G standards (FDD and TDD) from 698MHz to 2700MHz as well as an expanded range of signal bandwidths from 60MHz down to 1.2MHz. The SC2200 accepts single-ended RF signals to eliminate baluns and features a mirrored pinout facilitating design of both paths. The device uses the PA output and input signals to adaptively generate an optimized correction function to minimize the PA’s distortion. Using RF-domain analog signal processing enables the SC2200 to operate over wide bandwidths and with very low power consumption. The dual linearizer is optimized for high-performance MIMO applications, including small cells, active antenna, and distributed antenna systems.SC2200 and SC1894 RF Power Amplifier Linearizers RF Power Amplifier Linearization Technology ApplicationsAmplifier: Class A/AB, DohertyAverage PA Output Power Examples: Cellular Infrastructure: 27dBm to 40dBmBTS Amplifiers, RRH, Booster Amplifiers, Repeaters, Small Cells, Microcells, Picocells, DAS, AAS and MIMO SystemsCellular InfrastructurePA Process: LDMOS, GaN, HBT, GaAs and InGaPSingle/Multicarrier, Multistandard: CDMA/EVDO, TD-SCDMA, WiMAX, WCDMA/HSDPA, LTE, and TD-LTEWide Range of PAs and Output Power

The AD6649 is a mixed-signal intermediate frequency (IF) receiverconsisting of dual 14-bit, 250 MSPS ADCs and a wideband digitaldownconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.The dual ADC core features a multistage, differential pipelinedarchitecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digitaldownconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.The AD6649 receiver digitizes a wide spectrum of IF frequencies.Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.Flexible power-down options allow significant power savings,when desired.Programming for setup and control is accomplished using a 3-pinSPI-compatible serial interface.The AD6649 is available in a 64-lead LFCSP and is specified overthe industrial temperature range of −40°C to +85°C.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE General-purpose software radios Broadband data applicationsPRODUCT HIGHLIGHTS Integrated dual, 14-bit, 250 MSPS ADC. Integrated wideband decimation filter and 32-bit complex NCO. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz. SYNC input allows synchronization of multiple devices. 3-pin, 1.8V SPI port for register programming and register readback.

The AD8284 is an integrated analog front end designed for low cost, compact size, flexibility, and ease of use. It contains a 4-channel differential multiplexer (mux), a 1-channel low noise preamplifier (LNA) with a programmable gain amplifier (PGA) and an antialiasing filter (AAF), as well as one direct-to-ADC channel, all integrated with a single, 12-bit analog-to-digital converter (ADC). The AD8284 also incorporates a saturation detection circuit for high frequency overvoltage conditions that would otherwise be filtered by the AAF.The analog channel features a gain range of 17 dB to 35 dB in 6 dB increments, and an ADC with a conversion rate of up to 60 MSPS. The combined input referred voltage noise of the entire channel is 3.5 nV/√Hz at maximum gain. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.Fabricated in an advanced CMOS process, the AD8284 is available in a 10 mm × 10 mm, RoHS compliant, 64-lead TQFP. It is specified over the automotive temperature range of −40°C to +105°C.APPLICATIONS Automotive radar   Adaptive cruise control   Collision avoidance   Blind spot detection   Self-parking   Electronic bumper

The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines a RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9361 receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.

The two independent direct conversion receivers have state-of-the-art noise figure and linearity. Each receive (RX) subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9361 also has flexible manual gain modes that can be externally controlled. Two high dynamic range analog-to-digital converters (ADCs) per channel digitize the received I and Q signals and pass them through configurable decimation filters and 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at the appropriate sample rate.

The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best in class TX error vector magnitude (EVM) of <−40 dB, allowing significant system margin for the external power amplifier (PA) selection. The on-board transmit (TX) power monitor can be used as a power detector, enabling highly accurate TX power measurements.

The fully integrated phase-locked loops (PLLs) provide low power fractional-N frequency synthesis for all receive and transmit channels. Channel isolation, demanded by frequency division duplex (FDD) systems, is integrated into the design. All VCO and loop filter components are integrated.

The core of the AD9361 can be powered directly from a 1.3 V regulator. The IC is controlled via a standard 4-wire serial port and four real-time input/output control pins. Comprehensive power-down modes are included to minimize power consumption during normal use. The AD9361 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA).

Applications:

• Point to point communication systems
• Femtocell/picocell/microcell base stations
• General-purpose radio systems

Features:

• RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
• TX band: 47 MHz to 6.0 GHz
• RX band: 70 MHz to 6.0 GHz
• Supports TDD and FDD operation
• Tunable channel bandwidth: <200 kHz to 56 MHz
• Dual receivers: 6 differential
• Superior receiver sensitivity with a noise figure of 2 dB at 800 MHz LO
• RX gain control
• Real-time monitor and control signals for manual gain
• Independent automatic gain control
• Dual transmitters: 4 differential outputs
• Highly linear broadband transmitter
  
  • TX EVM: ≤−40 dB
  • TX noise: ≤−157 dBm/Hz noise floor
  • TX monitor: ≥66 dB dynamic range with 1 dB accuracy
• Integrated fractional-N synthesizers
• 2.4 Hz maximum local oscillator (LO) step size
• Multichip synchronization
• CMOS/LVDS digital interface

The LTC6431-15 is a gain-block amplifier with excellent linearity at frequencies beyond 1000MHz and with low associated output noise.The unique combination of high linearity, low noise and low power dissipation make this an ideal candidate for many signal-chain applications. The LTC6431-15 is easy to use, requiring a minimum of external components. It is internally input/output matched to 50Ω and it draws only 90mA from a single 5V supply.On-chip bias and temperature compensation maintain performance over environmental changes.The LTC6431-15 uses a high performance SiGe BiCMOS process for excellent repeatability compared with similar GaAs amplifiers. All A-grade LTC6431-15 devices are tested and guaranteed for OIP3 at 240MHz. The LTC6431-15 is housed in a 4mm x 4mm 24-lead QFN package with an exposed pad for thermal management and low inductance.Applications Single-Ended IF Amplifier ADC Driver CATV

The LTM9013 is a 300MHz wideband, low IF receiver. Utilizing an integrated system in a package (SiP) technology, it is a μModule® (micromodule) receiver that includes a dual high speed 14-bit A/D converter, lowpass filter, differential gain stages and a quadrature demodulator.The LTM9013 is perfect for wideband I/Q receiver applications, with AC performance that includes 59dB SNR and 1.3dB frequency flatness from DC to 300MHz. A highpass filter or simple AC coupling are used external to the device for design flexiblity. The integrated on-chip broadband transformers provide a 50Ω single-ended interface at the RF input.A 5V supply powers the demodulator and a 3.3V supply powers the IF amplifiers for minimal distortion. A 1.8V supply allows low power ADC operation. A separate output supply allows the DDR LVDS outputs to drive 1.8V logic. An optional multiplexer allows both channels to share a digital output bus. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.Applications Telecommunications Wideband, Low IF Receivers Digital Predistortion Receivers Cellular Base Stations

The ADF4001 frequency synthesizer can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator) or VCXO (Voltage Controlled Crystal Oscillator). The N min value of 1 allows flexibility in clock generation. 

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).