The HMC822LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC942LP4E is a x2 active broadband frequency multiplier utilizing GaAs pHEMT technology in a leadless RoHS compliant SMT package. When driven by a +4 dBm signal, the multiplier provides +17 dBm typical output power from 13 to 24.6 GHz. The Fo and 3Fo isolations are >20 dBc at 19 GHz. The HMC942LP4E is ideal for use in LO multiplier chains for Pt-to-Pt & VSAT Radios yielding reduced parts count vs. traditional approaches.APPLICATIONS Clock Generation Applications: SONET OC-192 & SDH STM-64 Point-to-Point & VSAT Radios Test Instrumentation Military & Space Sensors

The HMC967LP4E is a compact GaAs MMIC I/Q downconverter in a leadless RoHS compliant SM T package. This device provides a small signal conversion gain of 15 dB with a noise figure of 2.5 dB and 25 dBc of image rejection across the frequency band. The HMC967LP4E utilizes an LNA followed by an image reject mixer which is driven by an active x2 multiplier. The image reject mixer eliminates the need for a filter following the LNA, and removes thermal noise at the image frequency. I and Q mixer outputs are provided and an external 90? hybrid is needed to select the required sideband. The HMC967LP4E is a much smaller alternative to hybrid style image reject mixer downconverter assemblies, and is compatible with surface mount manufacturing techniques.Applications Point-to-Point &?Point-to-Multi-Point Radio Military Radar, EW & ELINT Satellite Communications

The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz.?The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package.?The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters.?Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution.?Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution.?With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures.?Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.?Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, SYNCINB?AB, and SYNCINB?CD input pins.?The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI.?The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the ?40?C to +105?C junction temperature range. Product Highlights Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers?3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios

The AD8339 is a quad I/Q demodulator configured to be driven by a low noise preamplifier with differential outputs. It is optimized for the LNA in the AD8332 / AD8334 / AD8335 family of VGAs. The part consists of four identical I/Q demodulators with a 4? local oscillator (LO) input that divides this signal and generates the necessary 0? and 90? phases of the internal LO that drive the mixers. The four I/Q demodulators can be used independently of each other (assuming that a common LO is acceptable) because each has a separate RF input.Continuous wave (CW) analog beamforming (ABF) and I/Q demodulation are combined in a single 40-lead ultracompact chip scale device, making the AD8339 particularly applicable in high density ultrasound scanners. In an ABF system, time domain coherency is achieved following the appropriate phase alignment and summation of multiple receiver channels. A reset pin synchronizes multiple ICs to start each LO divider in the same quadrant. Sixteen programmable 22.5? phase increments are available for each channel. For example, if Channel 1 is used as a reference and Channel 2 has an I/Q phase lead of 45?, then the user can phase align Channel 2 with Channel 1 by choosing the correct code.The mixer outputs are in current form for convenient summation. The independent I and Q mixer output currents are summed and converted to a voltage by a low noise, high dynamic range, current-to-voltage (I-V) transimpedance amplifier, such as the AD8021?or the AD829. Following the current summation, the combined signal is applied to a high resolution analog-to-digital converter (ADC), such as the AD7665?(16-bit, 570 kSPS).An SPI-compatible serial interface port is provided to easily program the phase of each channel; the interface allows daisy chaining by shifting the data through each chip from SDI to SDO. The SPI also allows for power-down of each individual channel and the complete chip. During power-down, the serial interface remains active so that the device can be programmed again.The dynamic range is typically 160 dB/Hz at the I and Q outputs. The AD8339 is available in a 6 mm ? 6 mm, 40-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.APPLICATIONS Medical imaging (CW ultrasound beamforming) Phased array systems Radar Adaptive antennas Communication receivers

The AD8341 vector modulator performs arbitrary amplitudeand phase modulation of an RF signal. Because the RF signalpath is linear, the original modulation is preserved. This part canbe used as a general-purpose RF modulator, a variable attenuator/phase shifter, or a remodulator. The amplitude can be controlledfrom a maximum of ?4.5 dB to less than ?34.5 dB, and the phasecan be shifted continuously over the entire 360? range. For maximumgain, the AD8341 delivers an OP1dB of 8.5 dBm, an OIP3of 17.5 dBm, and an output noise floor of ?150.5 dBm/Hz,independent of phase. It operates over a frequency range of1.5 GHz to 2.4 GHz.The baseband inputs in Cartesian I and Q format control theamplitude and phase modulation imposed on the RF inputsignal. Both I and Q inputs are dc-coupled with a ?500 mVdifferential full-scale range. The maximum modulationbandwidth is 230 MHz, which can be reduced by adding externalcapacitors to limit the noise bandwidth on the control lines.Both the RF inputs and outputs can be used differentially orsingle-ended and must be ac-coupled. The RF input and outputimpedances are nominally 50 ? over the operating frequencyrange. The DSOP pin allows the output stage to be disabledquickly in order to protect subsequent stages from overdrive.The AD8341 operates off supply voltages from 4.75 V to 5.25 Vwhile consuming approximately 125 mA.The AD8341 is fabricated on Analog Devices? proprietary, highperformance 25 GHz SOI complementary bipolar IC process. Itis available in a 24-lead, lead-free LFCSP package and operatesover a ?40?C to +85?C temperature range. Evaluation boardsare available. Applications RF PA linearization/RF predistortion Amplitude and phase modulation Variable attenuators and phase shifters CDMA2000, WCDMA, GSM/EDGE linear power amplifiers Smart antennasAvailabilitySamples part number AD8341ACP and an evaluation board, part number AD8341-EVAL, are available.Companion ProductsAD8302 - LF - 2.7GHz RF/IF Gain Phase DetectorAD8340 - RF Vector Modulator 700MHz to 1000MHzOther Modulator / Demodulator ProductsAD8345 - 250MHz to 1000MHz Low Noise RF/IF ModulatorAD8346 - 800MHz to 2.5GHz Lower Power Direct Up-Conversion ModulatorAD8347 - 800MHz to 2.7GHz Direct Conversion DemodulatorAD8348 - 50MHz to 1000MHz RF/IF Quadrature DemodulatorAD8349 - 700MHz - 2.7GHz Low Noise Direct Up Conversion Modulator

The AD8361 is a mean-responding power detector for use inhigh frequency receiver and transmitter signal chains, up to2.5 GHz. It is very easy to apply. It requires a single supply onlybetween 2.7 V and 5.5 V, a power supply decoupling capacitor,and an input coupling capacitor in most applications. Theoutput is a linear-responding dc voltage with a conversion gainof 7.5 V/V rms. An external filter capacitor can be added toincrease the averaging time constant.The AD8361 is intended for true power measurement of simpleand complex waveforms. The device is particularly useful formeasuring high crest-factor (high peak-to-rms ratio) signals,such as CDMA and W-CDMA.The AD8361 has three operating modes to accommodate avariety of analog-to-digital converter requirements: Ground reference mode, in which the origin is zero. Internal reference mode, which offsets the output 350 mV above ground. Supply reference mode, which offsets the output to VS/7.5.The AD8361 is specified for operation from ?40?C to +85?Cand is available in 8-lead MSOP and 6-lead SOT-23 packages. Itis fabricated on a proprietary high fT silicon bipolar process.

RF Development Tools Evaluation board for ADL5358

Phase Locked Loops - PLL WBand RF PLL VCO, 25-3000MHz

The HMC596LP4(E) is a low-cost 4x2 switch matrix in a leadless QFN 4x4 mm surface mount package for use in Satellite/DBS, LNBs and multiswitches from 200 to 3000 MHz. A positive voltage controlled 4 bit decoder is integrated on the switch. The switches may be used in either 75 ohm or 50 ohm systems.Both switch outputs (OP1 & OP2) can independently select any of the four inputs (HH, HL, VH, VL) or simultaneously select the same inputs. Note that the switch is bi-directional and input/output functionality may be interchanged. All data presented was measured in a 50 ohm (input/output) system.APPLICATIONS DBS LNBs & Multiswitches Cable Modem/CATV Cellular Systems