Dual, 12-Bit, 80 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter Features: 1.8 V supply operation Low power: 115 mW per channel at 125 MSPS with scalable power options SNR = 71 dBFS (to Nyquist) SFDR = 93 dBc at 70 MHz DNL = −0.1 LSB to +0.2 LSB (typical); INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) and low power, reduced range option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input voltage range Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Clock divider Programmable output clock and data alignment Programmable output resolution Standby mode

Quad 14-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface Features: High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range

Quad 16-/14-/12-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface

Quad, Current-Output, Serial-Input 16-/14-Bit DACs Features: 16-bit resolution INL of ±1 LSB (B Grade) 2 mA full-scale current ± 20%, with VREF = ±10 V 0.9 μs settling time to ±0.1% 12 MHz multiplying bandwidth Midscale glitch of −1 nV-sec Midscale or zero-scale reset Four separate, 4-quadrant multiplying reference inputs Compact 28-lead SSOP and 32-lead LFCSP See data sheet for additional featuresAD5544-EP supports defense and aerospace applications (AQEC standard) Download AD5544-EP Data Sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12663 DSCC Drawing Number

High Common-Mode Voltage, Single-Supply Difference Amplifier

Low Voltage Controller for Touch Screens Features: 4-wire touch screen interface 1.6 V to 3.6 V operation Median and averaging filter to reduce noise Automatic conversion sequencer and timer User-programmable conversion parameters Auxiliary analog input/battery monitor (0.5 V to 5 V) 1 optional GPIO Interrupt outputs (INT, PENIRQ) Touch-pressure measurement Wake-up on touch function Shutdown mode: 6 μA maximum 12-ball, 1.6 mm × 2 mm WLCSP 16-lead, 4 mm × 4 mm LFCSP

1.6 V, Micropower 12-/10-/8-Bit ADCs

20 V, 500 mA, Low Noise, CMOS LDO Features: Input voltage range: 3.3 V to 20 V Maximum output current: 500 mA Low Noise: 15 μV rms for fixed output versions PSRR Performance of 60 dB at 10 kHz, VOUT = 3.3 V Reverse current protection Low dropout voltage: 350 mV at 500 mA Initial accuracy: ±0.8% Accuracy over line, load, and temperature −2% to +1%, TJ = −40°C to +125°C −1.25% to +1%, TJ = 0°C to +85°C Low quiescent current (VIN = 5 V), IGND = 900 μA with 500 mA load Low shutdown current: <40 μA at VIN = 12 V, stable with small 1 μF ceramic output capacitor 7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 5 V, and 9 V Adjustable output from 1.22 V to VIN − VDO Foldback current limit and thermal overload protection User programmable precision UVLO/enable Power-good indicator 8-lead LFCSP and 8-lead SOIC packages

X-Stream 4.25 Gbps 40 40 Digital Crosspoint Switch Features: DC to 4.25 Gbps per port NRZ data rate Adjustable receive equalization 3 dB, 6 dB, or 12 dB boost Compensates over 40 inches of FR4 at 4.25 Gbps Adjustable transmit preemphasis/deemphasis Programmable boost and output level Compensates over 40 inches of FR4 at 4.25 Gbps Low Power 105 mW per channel at 2.5 V (400 mVP-P differential output level swing) 40 × 40, fully differential, nonblocking array Double rank connection programming with dual maps Low jitter, typically <25 ps Flexible 2.5 V to 3.3 V supply range DC- or ac-coupled differential PECL/CML inputs Differential CML outputs Per-lane polarity inversion for routing ease 50 Ω on-chip I/O termination with disable feature Supports 8b10b, scrambled or uncoded NRZ data Serial (I2C slave or SPI) control interface Parallel control interface

Cascadable IF VGAs with Programmable RMS Detectors