RF Detector Log Det Controller , 50 Hz - 3 GHz

RF Mixer DBL-BAL mix SMT, 4 - 8 GHz

Metering Systems on a Chip - SoC Highly Integrated Power and Energy IC

Metering Systems on a Chip - SoC 8 Out Sgl Phase Pwr & Energy Msrmt IC

Flyback Switching Regulator IC Positive or Negative, Isolation Capable 1 Output 135mA (Switch) 16-SOIC (0.154", 3.90mm Width)

2A, 36V DC/DC Step-Down Module (Power Module) Regulator Features:Complete Step-Down Switch Mode Power SupplyWide Input Voltage Range: 3.6V to 36V2A Output Current0.8V to 10V Output VoltageSelectable Switching Frequency: 200kHz to 2.4MHzCurrent Mode ControlProgrammable Soft-StartSnPb (BGA) or RoHS Compliant (LGA and BGA) FinishTiny, Low Profile, Surface Mount LGA (9mm × 11.25mm × 2.82mm) and BGA (9mm × 11.25mm × 3.42mm) Packages

General Purpose Amplifier 2 Circuit 8-SO

Low Input Bias Current, Wide BW JFET Precision Dual Op Amp Features: Low Noise 6 nV/√Hz Low Offset Voltage: 100 µV Max Low Input Bias Current 10 pA Max Fast Settling: 600 ns to 0.01% Low Distortion Unity Gain Stable No Phase Reversal Dual-Supply Operation: ±5 V to ±13 V

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

3000 V/S, 35mW Current Feedback Quad Amplifier Features: High speed 250 MHz -3 dB bandwidth (G = +1) 3000 V/µs slew rate 21 ns settling time to 0.1% 1.8 ns rise time for 2 V step Low power 3.5 mA/amp power supply Current (35 mW/amp) Single supply operation Fully specified for +5 V supply High output current of 50 mA Good video specifications (RL = 150 Ω, G = +2) Gain flatness 0.1 dB to 30 MHz 0.04% differential gain error 0.10° differential phase error Low distortion –78 dBc THD at 5 MHz –61 dBc THD at 20 MHz Available in a 14-lead SOIC