The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The AD9269 incorporates an optional integrated dc correction and quadrature error correction block (QEC) that corrects for dc offset, gain, and phase mismatch between the two channels. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers.The ADC also contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is pro-vided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR

The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The AD9269 incorporates an optional integrated dc correction and quadrature error correction block (QEC) that corrects for dc offset, gain, and phase mismatch between the two channels. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers.The ADC also contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is pro-vided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR

The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC). It is optimized for high performance over wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range.The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. The internal power-down feature supported via the SPI and typically consumes less than 5 mW when disabled.Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range. Product HighlightsIF optimization capability used to improve SFDR.Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture.Packaged in a Pb-free, 72-lead LFCSP package.Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths.Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS. ApplicationsMulticarrier, multimode cellular receiversAntenna array positioningPower amplifier linearizationBroadband wirelessRadarInfrared imagingCommunications instrumentation

The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.The AD9523 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free coarse timing adjustment in increments that are equal to the period of the signal coming out of the VCO.An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clockeven when all references have failed by means of a digitallycontrolled loop and holdover circuitry.The AD9548 operates over an industrial temperature range of−40°C to +85°C.ApplicationsNetwork synchronizationCleanup of reference clock jitterGPS 1 pulse per second synchronizationSONET/SDH clocks up to OC-192, including FECStratum 2 holdover, jitter cleanup, and phase transient controlStratum 3E and Stratum 3 reference clocksWireless base stations, controllersCable infrastructureData communications

The AD9629 is a monolithic, single channel 1.8 V supply, 12-bit, 20 MSPS/40 MSPS/65MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported.The AD9629 is available in a 32-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).Applications Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imagingProduct Highlights1. The AD9629 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.3. A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D11 to D0) timing and offset adjustments, and voltage reference modes.4. The AD9629 is packaged in a 32-lead RoHS compliant LFCSP that is pin compatible with the AD9609 10-bit ADC and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.

The AD9629 is a monolithic, single channel 1.8 V supply, 12-bit, 20 MSPS/40 MSPS/65MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported.The AD9629 is available in a 32-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).Applications Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imagingProduct Highlights1. The AD9629 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.3. A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D11 to D0) timing and offset adjustments, and voltage reference modes.4. The AD9629 is packaged in a 32-lead RoHS compliant LFCSP that is pin compatible with the AD9609 10-bit ADC and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.

The ADF41020 frequency synthesizer can be used to implement local oscillators as high as 18 GHz in the up conversion and down conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and high frequency programmable feedback dividers (A, B, and P). A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). The synthesizer can be used to drive external microwave VCOs via an active loop filter. Its very high bandwidth means a frequency doubler stage can be eliminated, simplifying system architecture and reducing cost. The ADF41020 is software-compatible with the existing ADF4106/ADF4107/ADF4108 family of devices from Analog Devices, Inc. Their pinouts match very closely with the exception of the ADF41020’s single-ended RF input pin, meaning only a minor layout change is required when updating current designs.Applications Microwave point-to-point/multipoint radios Wireless infrastructure VSAT radios Test equipment Instrumentation

Fast settling, highly accurate, low power, 8-/16-channel, multiplexed ADC for low bandwidth input signals with integrated input buffers.Integrated precision, 2.5 V, low drift (3.5 ppm/°C), band gap reference and integrated oscillator.Eight flexible setups with configurability for output data rate, digital filter mode, offset/gain error correction, reference selection, buffer enables and more. This per channel configurability extends to the output data rate used for each channel when using sinc5 + sinc1 filter.Sinc5 + sinc1 filter maximizes channel scan rate, and sinc3 filter maximizes resolution and enhanced 50 Hz/60 Hz rejection, with four selectable options to maximize rejection.Integrated diagnostic features, including CRC, register checksum, temperature sensor, crosspoint multiplexer, burnout currents, and GPIOs/GPOs.Applications Process control: PLC/DCS modules Voltage, current, temperature, and pressure measurement Flow meters Medical and scientific multichannel instrumentation Seismic instrumentation Chemical analysis instrumentation: chromatography

The ADAS3022 is a complete 16-bit, 1 MSPS, successive approximation–based analog-to-digital data acquisition system, which is manufactured on Analog Devices, Inc., proprietary iCMOS® high voltage industrial process technology. The device integrates an 8-channel, low leakage multiplexer; a high impedance programmable gain instrumentation amplifier (PGIA) stage with high common-mode rejection; a precision, low drift 4.096 V reference and buffer; and a 16-bit charge redistribution analog-to-digital converter (ADC) with successive approximation register (SAR) architecture. The ADAS3022 can resolve eight single-ended inputs or four fully differential inputs up to ±24.576 V when using ±15 V supplies. In addition, the device can accept the commonly used bipolar differential, bipolar single-ended, pseudo bipolar, or pseudo unipolar input signals, as shown in Table 1, thus enabling the use of almost any direct sensor interface.The ADAS3022 simplifies design challenges by eliminating signal buffering, level shifting, amplification/attenuation, common-mode rejection, settling time, and any other analog signal conditioning challenge while allowing a smaller form factor, faster time to market, and lower cost.APPLICATIONS  Multichannel data acquisition and system monitoring Process control Power line monitoring Automated test equipment Instrumentation